From: Sowjanya Komatineni <skomatineni@nvidia.com> To: thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, skomatineni@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com, devicetree@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-pm@vger.kernel.org Subject: [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate Date: Wed, 31 Jul 2019 14:10:46 -0700 [thread overview] Message-ID: <1564607463-28802-4-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1564607463-28802-1-git-send-email-skomatineni@nvidia.com> This patch implements context restore for clock divider. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So on resume, clock dividers are restored back for normal operation. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/clk/tegra/clk-divider.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index e76731fb7d69..ca0de5f11f84 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -109,10 +109,21 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static void clk_divider_restore_context(struct clk_hw *hw) +{ + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + unsigned long rate = clk_hw_get_rate(hw); + + if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0) + WARN_ON(1); +} + const struct clk_ops tegra_clk_frac_div_ops = { .recalc_rate = clk_frac_div_recalc_rate, .set_rate = clk_frac_div_set_rate, .round_rate = clk_frac_div_round_rate, + .restore_context = clk_divider_restore_context, }; struct clk *tegra_clk_register_divider(const char *name, -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <tglx@linutronix.de>, <jason@lakedaemon.net>, <marc.zyngier@arm.com>, <linus.walleij@linaro.org>, <stefan@agner.ch>, <mark.rutland@arm.com> Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>, <sboyd@kernel.org>, <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>, <josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>, <digetx@gmail.com>, <devicetree@vger.kernel.org>, <rjw@rjwysocki.net>, <viresh.kumar@linaro.org>, <linux-pm@vger.kernel.org> Subject: [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate Date: Wed, 31 Jul 2019 14:10:46 -0700 [thread overview] Message-ID: <1564607463-28802-4-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1564607463-28802-1-git-send-email-skomatineni@nvidia.com> This patch implements context restore for clock divider. During system suspend, core power goes off and looses the settings of the Tegra CAR controller registers. So on resume, clock dividers are restored back for normal operation. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/clk/tegra/clk-divider.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c index e76731fb7d69..ca0de5f11f84 100644 --- a/drivers/clk/tegra/clk-divider.c +++ b/drivers/clk/tegra/clk-divider.c @@ -109,10 +109,21 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static void clk_divider_restore_context(struct clk_hw *hw) +{ + struct clk_hw *parent = clk_hw_get_parent(hw); + unsigned long parent_rate = clk_hw_get_rate(parent); + unsigned long rate = clk_hw_get_rate(hw); + + if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0) + WARN_ON(1); +} + const struct clk_ops tegra_clk_frac_div_ops = { .recalc_rate = clk_frac_div_recalc_rate, .set_rate = clk_frac_div_set_rate, .round_rate = clk_frac_div_round_rate, + .restore_context = clk_divider_restore_context, }; struct clk *tegra_clk_register_divider(const char *name, -- 2.7.4
next prev parent reply other threads:[~2019-07-31 21:10 UTC|newest] Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-31 21:10 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-08-05 9:20 ` Linus Walleij 2019-08-05 9:20 ` Linus Walleij 2019-08-06 21:51 ` Sowjanya Komatineni 2019-08-06 21:51 ` Sowjanya Komatineni 2019-08-07 3:40 ` Sowjanya Komatineni 2019-08-07 3:40 ` Sowjanya Komatineni 2019-08-07 13:11 ` Linus Walleij 2019-08-07 13:11 ` Linus Walleij 2019-08-05 10:50 ` Dmitry Osipenko 2019-08-05 18:06 ` Sowjanya Komatineni 2019-08-05 18:06 ` Sowjanya Komatineni 2019-08-06 17:59 ` Dmitry Osipenko 2019-08-06 21:54 ` Sowjanya Komatineni 2019-08-06 21:54 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 02/20] pinctrl: tegra210: Add Tegra210 pinctrl pm ops Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-08-05 9:21 ` Linus Walleij 2019-08-05 9:21 ` Linus Walleij 2019-07-31 21:10 ` Sowjanya Komatineni [this message] 2019-07-31 21:10 ` [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 04/20] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 05/20] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 07/20] clk: tegra: clk-periph: Add save and restore support Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 08/20] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 09/20] clk: tegra: clk-super: Add save and restore support Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 10/20] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-08-01 10:18 ` Dmitry Osipenko 2019-08-01 10:37 ` Dmitry Osipenko 2019-08-01 16:10 ` Sowjanya Komatineni 2019-08-01 17:10 ` Dmitry Osipenko 2019-08-01 17:10 ` Dmitry Osipenko 2019-08-01 17:53 ` Sowjanya Komatineni 2019-08-01 17:53 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 11/20] cpufreq: tegra124: " Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-08-01 5:40 ` Viresh Kumar 2019-08-01 17:51 ` Sowjanya Komatineni 2019-08-01 17:51 ` Sowjanya Komatineni 2019-08-02 3:41 ` Viresh Kumar 2019-07-31 21:10 ` [PATCH v7 12/20] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 13/20] clk: tegra210: Add suspend and resume support Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 14/20] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 15/20] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:10 ` [PATCH v7 16/20] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni 2019-07-31 21:10 ` Sowjanya Komatineni 2019-07-31 21:11 ` [PATCH v7 17/20] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni 2019-07-31 21:11 ` Sowjanya Komatineni 2019-07-31 21:11 ` [PATCH v7 18/20] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni 2019-07-31 21:11 ` Sowjanya Komatineni 2019-07-31 21:11 ` [PATCH v7 19/20] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni 2019-07-31 21:11 ` Sowjanya Komatineni 2019-07-31 21:11 ` [PATCH v7 20/20] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni 2019-07-31 21:11 ` Sowjanya Komatineni -- strict thread matches above, loose matches on Subject: below -- 2019-07-31 0:20 [PATCH v7 00/20] SC7 entry and exit support for Tegra210 Sowjanya Komatineni 2019-07-31 0:20 ` [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni 2019-07-31 0:20 ` Sowjanya Komatineni 2019-07-31 10:49 ` Dmitry Osipenko
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