From: Sowjanya Komatineni <skomatineni@nvidia.com> To: thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com Cc: pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com, skomatineni@nvidia.com, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, mperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com, devicetree@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, linux-pm@vger.kernel.org Subject: [PATCH v9 19/22] soc/tegra: pmc: Configure core power request polarity Date: Fri, 16 Aug 2019 12:42:04 -0700 [thread overview] Message-ID: <1565984527-5272-20-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1565984527-5272-1-git-send-email-skomatineni@nvidia.com> This patch configures polarity of the core power request signal in PMC control register based on the device tree property. PMC asserts and de-asserts power request signal based on it polarity when it need to power-up and power-down the core rail during SC7. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/soc/tegra/pmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 76e7292ded25..53ed70773872 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -56,6 +56,7 @@ #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ +#define PMC_CNTRL_PWRREQ_POLARITY BIT(8) #define PMC_CNTRL_MAIN_RST BIT(4) #define PMC_WAKE_MASK 0x0c @@ -2290,6 +2291,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) else value |= PMC_CNTRL_SYSCLK_POLARITY; + if (pmc->corereq_high) + value &= ~PMC_CNTRL_PWRREQ_POLARITY; + else + value |= PMC_CNTRL_PWRREQ_POLARITY; + /* configure the output polarity while the request is tristated */ tegra_pmc_writel(pmc, value, PMC_CNTRL); -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <tglx@linutronix.de>, <jason@lakedaemon.net>, <marc.zyngier@arm.com>, <linus.walleij@linaro.org>, <stefan@agner.ch>, <mark.rutland@arm.com> Cc: <pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>, <sboyd@kernel.org>, <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>, <josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>, <digetx@gmail.com>, <devicetree@vger.kernel.org>, <rjw@rjwysocki.net>, <viresh.kumar@linaro.org>, <linux-pm@vger.kernel.org> Subject: [PATCH v9 19/22] soc/tegra: pmc: Configure core power request polarity Date: Fri, 16 Aug 2019 12:42:04 -0700 [thread overview] Message-ID: <1565984527-5272-20-git-send-email-skomatineni@nvidia.com> (raw) In-Reply-To: <1565984527-5272-1-git-send-email-skomatineni@nvidia.com> This patch configures polarity of the core power request signal in PMC control register based on the device tree property. PMC asserts and de-asserts power request signal based on it polarity when it need to power-up and power-down the core rail during SC7. Reviewed-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/soc/tegra/pmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 76e7292ded25..53ed70773872 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -56,6 +56,7 @@ #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ +#define PMC_CNTRL_PWRREQ_POLARITY BIT(8) #define PMC_CNTRL_MAIN_RST BIT(4) #define PMC_WAKE_MASK 0x0c @@ -2290,6 +2291,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc) else value |= PMC_CNTRL_SYSCLK_POLARITY; + if (pmc->corereq_high) + value &= ~PMC_CNTRL_PWRREQ_POLARITY; + else + value |= PMC_CNTRL_PWRREQ_POLARITY; + /* configure the output polarity while the request is tristated */ tegra_pmc_writel(pmc, value, PMC_CNTRL); -- 2.7.4
next prev parent reply other threads:[~2019-08-16 19:42 UTC|newest] Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-08-16 19:41 [PATCH v9 00/22] SC7 entry and exit support for Tegra210 Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 01/22] pinctrl: tegra: Fix write barrier placement in pmx_writel Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-18 22:20 ` Linus Walleij 2019-08-18 22:20 ` Linus Walleij 2019-08-16 19:41 ` [PATCH v9 02/22] pinctrl: tegra: Flush pinctrl writes during resume Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-18 22:20 ` Linus Walleij 2019-08-18 22:20 ` Linus Walleij 2019-08-16 19:41 ` [PATCH v9 03/22] clk: tegra: divider: Save and restore divider rate Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 04/22] clk: tegra: pllout: Save and restore pllout context Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 05/22] clk: tegra: pll: Save and restore pll context Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 06/22] clk: tegra: Support for OSC context save and restore Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 07/22] clk: Add API to get index of the clock parent Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-06 23:10 ` Stephen Boyd 2019-11-06 23:10 ` Stephen Boyd 2019-11-07 0:54 ` Dmitry Osipenko 2019-11-07 15:21 ` Thierry Reding 2019-11-07 19:19 ` Stephen Boyd 2019-11-08 10:11 ` Thierry Reding 2019-11-08 18:12 ` Stephen Boyd 2019-11-08 18:55 ` Thierry Reding 2019-11-08 21:15 ` Stephen Boyd 2019-08-16 19:41 ` [PATCH v9 08/22] clk: tegra: periph: Add restore_context support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 09/22] clk: tegra: clk-super: Fix to enable PLLP branches to CPU Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 10/22] clk: tegra: clk-super: Add restore-context support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 11/22] clk: tegra: clk-dfll: Add suspend and resume support Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-08 21:20 ` Stephen Boyd 2019-11-08 21:20 ` Stephen Boyd 2019-11-08 23:38 ` Dmitry Osipenko 2019-08-16 19:41 ` [PATCH v9 12/22] cpufreq: tegra124: " Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-11-02 14:42 ` Thierry Reding 2019-11-02 14:42 ` Thierry Reding 2019-08-16 19:41 ` [PATCH v9 13/22] clk: tegra210: Use fence_udelay during PLLU init Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:41 ` [PATCH v9 14/22] clk: tegra: Share clk and rst register defines with Tegra clock driver Sowjanya Komatineni 2019-08-16 19:41 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 15/22] clk: tegra210: Add suspend and resume support Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-19 16:47 ` Dmitry Osipenko 2019-08-16 19:42 ` [PATCH v9 16/22] soc/tegra: pmc: Allow to support more tegras wake Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 17/22] soc/tegra: pmc: Add pmc wake support for tegra210 Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 18/22] arm64: tegra: Enable wake from deep sleep on RTC alarm Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni [this message] 2019-08-16 19:42 ` [PATCH v9 19/22] soc/tegra: pmc: Configure core power request polarity Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 20/22] soc/tegra: pmc: Configure deep sleep control settings Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-19 16:48 ` Dmitry Osipenko 2019-08-19 18:20 ` Sowjanya Komatineni 2019-08-19 18:20 ` Sowjanya Komatineni 2019-08-19 19:07 ` Sowjanya Komatineni 2019-08-19 19:07 ` Sowjanya Komatineni 2019-08-19 19:33 ` Dmitry Osipenko 2019-08-16 19:42 ` [PATCH v9 21/22] arm64: dts: tegra210-p2180: Jetson TX1 SC7 timings Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni 2019-08-16 19:42 ` [PATCH v9 22/22] arm64: dts: tegra210-p3450: Jetson Nano " Sowjanya Komatineni 2019-08-16 19:42 ` Sowjanya Komatineni
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