From: Elaine Zhang <zhangqing@rock-chips.com>
To: heiko@sntech.de
Cc: mturquette@baylibre.com, sboyd@kernel.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
xxx@rock-chips.com, xf@rock-chips.com, huangtao@rock-chips.com,
Elaine Zhang <zhangqing@rock-chips.com>
Subject: [PATCH v3 2/5] clk: rockchip: fix up the frac clk get rate error
Date: Fri, 27 Sep 2019 11:00:41 +0800 [thread overview]
Message-ID: <1569553244-3165-3-git-send-email-zhangqing@rock-chips.com> (raw)
In-Reply-To: <1569553244-3165-1-git-send-email-zhangqing@rock-chips.com>
support fractional divider with only one level parent clock
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fac5a4a3f5c3..8f77c3f9fab7 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -190,16 +190,21 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
- p_parent_rate = clk_hw_get_rate(p_parent);
- *parent_rate = p_parent_rate;
- if (fd->max_prate && p_parent_rate > fd->max_prate) {
- div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
- *parent_rate = p_parent_rate / div;
+ if (!p_parent) {
+ *parent_rate = p_rate;
+ } else {
+ p_parent_rate = clk_hw_get_rate(p_parent);
+ *parent_rate = p_parent_rate;
+ if (fd->max_prate && p_parent_rate > fd->max_prate) {
+ div = DIV_ROUND_UP(p_parent_rate,
+ fd->max_prate);
+ *parent_rate = p_parent_rate / div;
+ }
}
if (*parent_rate < rate * 20) {
- pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n",
- clk_hw_get_name(hw), *parent_rate, rate);
+ pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
+ clk_hw_get_name(hw), *parent_rate, rate);
*m = 0;
*n = 1;
return;
--
1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Elaine Zhang <zhangqing@rock-chips.com>
To: heiko@sntech.de
Cc: huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com,
sboyd@kernel.org, mturquette@baylibre.com,
Elaine Zhang <zhangqing@rock-chips.com>,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/5] clk: rockchip: fix up the frac clk get rate error
Date: Fri, 27 Sep 2019 11:00:41 +0800 [thread overview]
Message-ID: <1569553244-3165-3-git-send-email-zhangqing@rock-chips.com> (raw)
In-Reply-To: <1569553244-3165-1-git-send-email-zhangqing@rock-chips.com>
support fractional divider with only one level parent clock
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fac5a4a3f5c3..8f77c3f9fab7 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -190,16 +190,21 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
- p_parent_rate = clk_hw_get_rate(p_parent);
- *parent_rate = p_parent_rate;
- if (fd->max_prate && p_parent_rate > fd->max_prate) {
- div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
- *parent_rate = p_parent_rate / div;
+ if (!p_parent) {
+ *parent_rate = p_rate;
+ } else {
+ p_parent_rate = clk_hw_get_rate(p_parent);
+ *parent_rate = p_parent_rate;
+ if (fd->max_prate && p_parent_rate > fd->max_prate) {
+ div = DIV_ROUND_UP(p_parent_rate,
+ fd->max_prate);
+ *parent_rate = p_parent_rate / div;
+ }
}
if (*parent_rate < rate * 20) {
- pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n",
- clk_hw_get_name(hw), *parent_rate, rate);
+ pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
+ clk_hw_get_name(hw), *parent_rate, rate);
*m = 0;
*n = 1;
return;
--
1.9.1
WARNING: multiple messages have this Message-ID (diff)
From: Elaine Zhang <zhangqing@rock-chips.com>
To: heiko@sntech.de
Cc: huangtao@rock-chips.com, xxx@rock-chips.com, xf@rock-chips.com,
sboyd@kernel.org, mturquette@baylibre.com,
Elaine Zhang <zhangqing@rock-chips.com>,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/5] clk: rockchip: fix up the frac clk get rate error
Date: Fri, 27 Sep 2019 11:00:41 +0800 [thread overview]
Message-ID: <1569553244-3165-3-git-send-email-zhangqing@rock-chips.com> (raw)
In-Reply-To: <1569553244-3165-1-git-send-email-zhangqing@rock-chips.com>
support fractional divider with only one level parent clock
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index fac5a4a3f5c3..8f77c3f9fab7 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -190,16 +190,21 @@ static void rockchip_fractional_approximation(struct clk_hw *hw,
if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
(fd->max_prate && fd->max_prate < p_rate)) {
p_parent = clk_hw_get_parent(clk_hw_get_parent(hw));
- p_parent_rate = clk_hw_get_rate(p_parent);
- *parent_rate = p_parent_rate;
- if (fd->max_prate && p_parent_rate > fd->max_prate) {
- div = DIV_ROUND_UP(p_parent_rate, fd->max_prate);
- *parent_rate = p_parent_rate / div;
+ if (!p_parent) {
+ *parent_rate = p_rate;
+ } else {
+ p_parent_rate = clk_hw_get_rate(p_parent);
+ *parent_rate = p_parent_rate;
+ if (fd->max_prate && p_parent_rate > fd->max_prate) {
+ div = DIV_ROUND_UP(p_parent_rate,
+ fd->max_prate);
+ *parent_rate = p_parent_rate / div;
+ }
}
if (*parent_rate < rate * 20) {
- pr_err("%s parent_rate(%ld) is low than rate(%ld)*20, fractional div is not allowed\n",
- clk_hw_get_name(hw), *parent_rate, rate);
+ pr_warn("%s p_rate(%ld) is low than rate(%ld)*20, use integer or half-div\n",
+ clk_hw_get_name(hw), *parent_rate, rate);
*m = 0;
*n = 1;
return;
--
1.9.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2019-09-27 3:08 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-27 3:00 [PATCH v3 0/5] clk: rockchip: Support for some new features Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-09-27 3:00 ` [PATCH v3 1/5] clk: rockchip: Add supprot to limit input rate for fractional divider Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-10-03 18:10 ` Stephen Boyd
2019-10-03 18:10 ` Stephen Boyd
2019-10-03 18:10 ` Stephen Boyd
2019-09-27 3:00 ` Elaine Zhang [this message]
2019-09-27 3:00 ` [PATCH v3 2/5] clk: rockchip: fix up the frac clk get rate error Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-10-03 18:11 ` Stephen Boyd
2019-10-03 18:11 ` Stephen Boyd
2019-10-03 18:11 ` Stephen Boyd
2019-09-27 3:00 ` [PATCH v3 3/5] clk: rockchip: add a clock-type for muxes based in the pmugrf Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-09-27 3:00 ` [PATCH v3 4/5] clk: rockchip: add pll up and down when change pll freq Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-09-27 3:00 ` Elaine Zhang
2019-10-03 18:13 ` Stephen Boyd
2019-10-03 18:13 ` Stephen Boyd
2019-10-03 18:13 ` Stephen Boyd
2019-09-27 3:01 ` [PATCH v3 5/5] clk: rockchip: support pll setting by auto Elaine Zhang
2019-09-27 3:01 ` Elaine Zhang
2019-09-27 3:01 ` Elaine Zhang
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