From: Liu Yi L <yi.l.liu@intel.com> To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Cc: pbonzini@redhat.com, mst@redhat.com, eric.auger@redhat.com, david@gibson.dropbear.id.au, kevin.tian@intel.com, yi.l.liu@intel.com, jun.j.tian@intel.com, yi.y.sun@intel.com, kvm@vger.kernel.org, Jacob Pan <jacob.jun.pan@linux.intel.com>, Yi Sun <yi.y.sun@linux.intel.com>, Richard Henderson <rth@twiddle.net>, Eduardo Habkost <ehabkost@redhat.com> Subject: [RFC v3.1 19/22] intel_iommu: process PASID-based iotlb invalidation Date: Sat, 22 Feb 2020 00:07:20 -0800 [thread overview] Message-ID: <1582358843-51931-20-git-send-email-yi.l.liu@intel.com> (raw) In-Reply-To: <1582358843-51931-1-git-send-email-yi.l.liu@intel.com> This patch adds the basic PASID-based iotlb (piotlb) invalidation support. piotlb is used during walking Intel VT-d 1st level page table. This patch only adds the basic processing. Detailed handling will be added in next patch. Cc: Kevin Tian <kevin.tian@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Peter Xu <peterx@redhat.com> Cc: Yi Sun <yi.y.sun@linux.intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> --- hw/i386/intel_iommu.c | 57 ++++++++++++++++++++++++++++++++++++++++++ hw/i386/intel_iommu_internal.h | 13 ++++++++++ 2 files changed, 70 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cacc38b..b712eae 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3157,6 +3157,59 @@ static bool vtd_process_pasid_desc(IntelIOMMUState *s, return (ret == 0) ? true : false; } +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, + uint16_t domain_id, + uint32_t pasid) +{ +} + +static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id, + uint32_t pasid, hwaddr addr, uint8_t am, bool ih) +{ +} + +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t domain_id; + uint32_t pasid; + uint8_t am; + hwaddr addr; + + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + + domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); + pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); + break; + + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: + am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); + addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); + if (am > VTD_MAMV) { + error_report_once("Invalid am, > max am value, hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + vtd_piotlb_page_invalidate(s, domain_id, pasid, + addr, am, VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1])); + break; + + default: + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + return true; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -3271,6 +3324,10 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) break; case VTD_INV_DESC_PIOTLB: + trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); + if (!vtd_process_piotlb_desc(s, &inv_desc)) { + return false; + } break; case VTD_INV_DESC_WAIT: diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index d427895..17c6e84 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -457,6 +457,19 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4) #define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4) +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) + +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL + +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ + VTD_DOMAIN_ID_MASK) +#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL) +#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL) +#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1) + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Liu Yi L <yi.l.liu@intel.com> To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Cc: kevin.tian@intel.com, yi.l.liu@intel.com, Yi Sun <yi.y.sun@linux.intel.com>, Eduardo Habkost <ehabkost@redhat.com>, kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com, eric.auger@redhat.com, yi.y.sun@intel.com, Jacob Pan <jacob.jun.pan@linux.intel.com>, pbonzini@redhat.com, Richard Henderson <rth@twiddle.net>, david@gibson.dropbear.id.au Subject: [RFC v3.1 19/22] intel_iommu: process PASID-based iotlb invalidation Date: Sat, 22 Feb 2020 00:07:20 -0800 [thread overview] Message-ID: <1582358843-51931-20-git-send-email-yi.l.liu@intel.com> (raw) In-Reply-To: <1582358843-51931-1-git-send-email-yi.l.liu@intel.com> This patch adds the basic PASID-based iotlb (piotlb) invalidation support. piotlb is used during walking Intel VT-d 1st level page table. This patch only adds the basic processing. Detailed handling will be added in next patch. Cc: Kevin Tian <kevin.tian@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Peter Xu <peterx@redhat.com> Cc: Yi Sun <yi.y.sun@linux.intel.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Liu Yi L <yi.l.liu@intel.com> --- hw/i386/intel_iommu.c | 57 ++++++++++++++++++++++++++++++++++++++++++ hw/i386/intel_iommu_internal.h | 13 ++++++++++ 2 files changed, 70 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cacc38b..b712eae 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3157,6 +3157,59 @@ static bool vtd_process_pasid_desc(IntelIOMMUState *s, return (ret == 0) ? true : false; } +static void vtd_piotlb_pasid_invalidate(IntelIOMMUState *s, + uint16_t domain_id, + uint32_t pasid) +{ +} + +static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id, + uint32_t pasid, hwaddr addr, uint8_t am, bool ih) +{ +} + +static bool vtd_process_piotlb_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t domain_id; + uint32_t pasid; + uint8_t am; + hwaddr addr; + + if ((inv_desc->val[0] & VTD_INV_DESC_PIOTLB_RSVD_VAL0) || + (inv_desc->val[1] & VTD_INV_DESC_PIOTLB_RSVD_VAL1)) { + error_report_once("non-zero-field-in-piotlb_inv_desc hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + + domain_id = VTD_INV_DESC_PIOTLB_DID(inv_desc->val[0]); + pasid = VTD_INV_DESC_PIOTLB_PASID(inv_desc->val[0]); + switch (inv_desc->val[0] & VTD_INV_DESC_IOTLB_G) { + case VTD_INV_DESC_PIOTLB_ALL_IN_PASID: + vtd_piotlb_pasid_invalidate(s, domain_id, pasid); + break; + + case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: + am = VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); + addr = (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); + if (am > VTD_MAMV) { + error_report_once("Invalid am, > max am value, hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + vtd_piotlb_page_invalidate(s, domain_id, pasid, + addr, am, VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1])); + break; + + default: + error_report_once("Invalid granularity in P-IOTLB desc hi: 0x%" PRIx64 + " lo: 0x%" PRIx64, inv_desc->val[1], inv_desc->val[0]); + return false; + } + return true; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -3271,6 +3324,10 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) break; case VTD_INV_DESC_PIOTLB: + trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); + if (!vtd_process_piotlb_desc(s, &inv_desc)) { + return false; + } break; case VTD_INV_DESC_WAIT: diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index d427895..17c6e84 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -457,6 +457,19 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PASIDC_PASID_SI (1ULL << 4) #define VTD_INV_DESC_PASIDC_GLOBAL (3ULL << 4) +#define VTD_INV_DESC_PIOTLB_ALL_IN_PASID (2ULL << 4) +#define VTD_INV_DESC_PIOTLB_PSI_IN_PASID (3ULL << 4) + +#define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000ffc0ULL +#define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL + +#define VTD_INV_DESC_PIOTLB_PASID(val) (((val) >> 32) & 0xfffffULL) +#define VTD_INV_DESC_PIOTLB_DID(val) (((val) >> 16) & \ + VTD_DOMAIN_ID_MASK) +#define VTD_INV_DESC_PIOTLB_ADDR(val) ((val) & ~0xfffULL) +#define VTD_INV_DESC_PIOTLB_AM(val) ((val) & 0x3fULL) +#define VTD_INV_DESC_PIOTLB_IH(val) (((val) >> 6) & 0x1) + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; -- 2.7.4
next prev parent reply other threads:[~2020-02-22 8:02 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-02-22 8:07 [RFC v3.1 00/22] intel_iommu: expose Shared Virtual Addressing to VMs Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 01/22] scripts/update-linux-headers: Import iommu.h Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 02/22] header file update VFIO/IOMMU vSVA APIs Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 03/22] vfio: check VFIO_TYPE1_NESTING_IOMMU support Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 04/22] hw/iommu: introduce HostIOMMUContext Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 05/22] hw/pci: add pci_device_setup_iommu Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 06/22] vfio/pci: init HostIOMMUContext per-container Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 07/22] vfio: get nesting iommu cap info from Kernel Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 08/22] vfio/common: add pasid_alloc/free support Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 09/22] hw/pci: add pci_device_host_iommu_context() Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 10/22] intel_iommu: add virtual command capability support Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 11/22] intel_iommu: process pasid cache invalidation Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 12/22] intel_iommu: add PASID cache management infrastructure Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 13/22] vfio: add bind stage-1 page table support Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 14/22] intel_iommu: bind/unbind guest page table to host Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 15/22] intel_iommu: replay guest pasid bindings " Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 16/22] intel_iommu: replay pasid binds after context cache invalidation Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 17/22] intel_iommu: do not pass down pasid bind for PASID #0 Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 18/22] vfio/common: add support for flush iommu stage-1 cache Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` Liu Yi L [this message] 2020-02-22 8:07 ` [RFC v3.1 19/22] intel_iommu: process PASID-based iotlb invalidation Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 20/22] intel_iommu: propagate PASID-based iotlb invalidation to host Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 21/22] intel_iommu: process PASID-based Device-TLB invalidation Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:07 ` [RFC v3.1 22/22] intel_iommu: modify x-scalable-mode to be string option Liu Yi L 2020-02-22 8:07 ` Liu Yi L 2020-02-22 8:21 ` [RFC v3.1 00/22] intel_iommu: expose Shared Virtual Addressing to VMs no-reply 2020-02-22 8:21 ` no-reply
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