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From: Mason Yang <masonccyang@mxic.com.tw>
To: broonie@kernel.org, tudor.ambarus@microchip.com,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	boris.brezillon@collabora.com, matthias.bgg@gmail.com
Cc: p.yadav@ti.com, juliensu@mxic.com.tw,
	linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org,
	linux-spi@vger.kernel.org
Subject: [PATCH v3 11/14] mtd: spi-nor: core: enable octal DTR mode when possible
Date: Thu, 28 May 2020 15:58:13 +0800	[thread overview]
Message-ID: <1590652696-8844-12-git-send-email-masonccyang@mxic.com.tw> (raw)
In-Reply-To: <1590652696-8844-1-git-send-email-masonccyang@mxic.com.tw>

From: Pratyush Yadav <p.yadav@ti.com>

Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/mtd/spi-nor/core.c | 35 +++++++++++++++++++++++++++++++++++
 drivers/mtd/spi-nor/core.h |  2 ++
 2 files changed, 37 insertions(+)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index cbfdf544..a353830 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3162,6 +3162,35 @@ static int spi_nor_init_params(struct spi_nor *nor)
 	return 0;
 }
 
+/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
+ * @nor:                 pointer to a 'struct spi_nor'
+ * @enable:              whether to enable or disable Octal DTR
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
+{
+	int ret;
+
+	if (!nor->params->octal_dtr_enable)
+		return 0;
+
+	if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
+	      nor->write_proto == SNOR_PROTO_8_8_8_DTR))
+		return 0;
+
+	ret = nor->params->octal_dtr_enable(nor, enable);
+	if (ret)
+		return ret;
+
+	if (enable)
+		nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+	else
+		nor->reg_proto = SNOR_PROTO_1_1_1;
+
+	return 0;
+}
+
 /**
  * spi_nor_quad_enable() - enable Quad I/O if needed.
  * @nor:                pointer to a 'struct spi_nor'
@@ -3201,6 +3230,12 @@ static int spi_nor_init(struct spi_nor *nor)
 {
 	int err;
 
+	err = spi_nor_octal_dtr_enable(nor, true);
+	if (err) {
+		dev_dbg(nor->dev, "octal mode not supported\n");
+		return err;
+	}
+
 	err = spi_nor_quad_enable(nor);
 	if (err) {
 		dev_dbg(nor->dev, "quad mode not supported\n");
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 91bc69a..9b0e0ba 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -223,6 +223,7 @@ struct cmd_seq_octal_dtr {
  * @erase_map:		the erase map parsed from the SFDP Sector Map Parameter
  *                      Table.
  * @cmd_seq:		command sequence to change to octal DTR mode.
+ * @octal_dtr_enable:	enables SPI NOR octal DTR mode.
  * @quad_enable:	enables SPI NOR quad mode.
  * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
  * @convert_addr:	converts an absolute address into something the flash
@@ -252,6 +253,7 @@ struct spi_nor_flash_parameter {
 
 	struct cmd_seq_octal_dtr	cmd_seq[4];
 
+	int (*octal_dtr_enable)(struct spi_nor *nor, bool enable);
 	int (*quad_enable)(struct spi_nor *nor);
 	int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
 	u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
-- 
1.9.1


WARNING: multiple messages have this Message-ID (diff)
From: Mason Yang <masonccyang@mxic.com.tw>
To: broonie@kernel.org, tudor.ambarus@microchip.com,
	miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
	boris.brezillon@collabora.com, matthias.bgg@gmail.com
Cc: juliensu@mxic.com.tw, linux-spi@vger.kernel.org,
	linux-mtd@lists.infradead.org, p.yadav@ti.com,
	linux-kernel@vger.kernel.org
Subject: [PATCH v3 11/14] mtd: spi-nor: core: enable octal DTR mode when possible
Date: Thu, 28 May 2020 15:58:13 +0800	[thread overview]
Message-ID: <1590652696-8844-12-git-send-email-masonccyang@mxic.com.tw> (raw)
In-Reply-To: <1590652696-8844-1-git-send-email-masonccyang@mxic.com.tw>

From: Pratyush Yadav <p.yadav@ti.com>

Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
 drivers/mtd/spi-nor/core.c | 35 +++++++++++++++++++++++++++++++++++
 drivers/mtd/spi-nor/core.h |  2 ++
 2 files changed, 37 insertions(+)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index cbfdf544..a353830 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3162,6 +3162,35 @@ static int spi_nor_init_params(struct spi_nor *nor)
 	return 0;
 }
 
+/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed
+ * @nor:                 pointer to a 'struct spi_nor'
+ * @enable:              whether to enable or disable Octal DTR
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
+{
+	int ret;
+
+	if (!nor->params->octal_dtr_enable)
+		return 0;
+
+	if (!(nor->read_proto == SNOR_PROTO_8_8_8_DTR &&
+	      nor->write_proto == SNOR_PROTO_8_8_8_DTR))
+		return 0;
+
+	ret = nor->params->octal_dtr_enable(nor, enable);
+	if (ret)
+		return ret;
+
+	if (enable)
+		nor->reg_proto = SNOR_PROTO_8_8_8_DTR;
+	else
+		nor->reg_proto = SNOR_PROTO_1_1_1;
+
+	return 0;
+}
+
 /**
  * spi_nor_quad_enable() - enable Quad I/O if needed.
  * @nor:                pointer to a 'struct spi_nor'
@@ -3201,6 +3230,12 @@ static int spi_nor_init(struct spi_nor *nor)
 {
 	int err;
 
+	err = spi_nor_octal_dtr_enable(nor, true);
+	if (err) {
+		dev_dbg(nor->dev, "octal mode not supported\n");
+		return err;
+	}
+
 	err = spi_nor_quad_enable(nor);
 	if (err) {
 		dev_dbg(nor->dev, "quad mode not supported\n");
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 91bc69a..9b0e0ba 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -223,6 +223,7 @@ struct cmd_seq_octal_dtr {
  * @erase_map:		the erase map parsed from the SFDP Sector Map Parameter
  *                      Table.
  * @cmd_seq:		command sequence to change to octal DTR mode.
+ * @octal_dtr_enable:	enables SPI NOR octal DTR mode.
  * @quad_enable:	enables SPI NOR quad mode.
  * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode.
  * @convert_addr:	converts an absolute address into something the flash
@@ -252,6 +253,7 @@ struct spi_nor_flash_parameter {
 
 	struct cmd_seq_octal_dtr	cmd_seq[4];
 
+	int (*octal_dtr_enable)(struct spi_nor *nor, bool enable);
 	int (*quad_enable)(struct spi_nor *nor);
 	int (*set_4byte_addr_mode)(struct spi_nor *nor, bool enable);
 	u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
-- 
1.9.1


______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

  parent reply	other threads:[~2020-05-28  7:59 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-28  7:58 [PATCH v3 00/14] mtd: spi-nor: add xSPI Octal DTR support Mason Yang
2020-05-28  7:58 ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 01/14] spi: spi-mem: allow specifying whether an op is DTR or not Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 02/14] spi: spi-mem: allow specifying a command's extension Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 03/14] mtd: spi-nor: add support for DTR protocol Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 04/14] mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 05/14] mtd: spi-nor: sfdp: get command opcode extension type from BFPT Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 06/14] mtd: spi-nor: sfdp: get octal mode maximum speed " Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 07/14] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 08/14] mtd: spi-nor: sfdp: parse command sequences to change octal DTR mode Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 09/14] mtd: spi-nor: core: add configuration register 2 read & write support Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 10/14] mtd: spi-nor: core: use dummy cycle and address width info from SFDP Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` Mason Yang [this message]
2020-05-28  7:58   ` [PATCH v3 11/14] mtd: spi-nor: core: enable octal DTR mode when possible Mason Yang
2020-05-28  7:58 ` [PATCH v3 12/14] spi: mxic: patch for octal DTR mode support Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28 21:44   ` kbuild test robot
2020-05-28 21:44     ` kbuild test robot
2020-05-28 21:44     ` kbuild test robot
2020-05-28  7:58 ` [PATCH v3 13/14] mtd: spi-nor: core: execute command sequences to change octal DTR mode Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  7:58 ` [PATCH v3 14/14] mtd: spi-nor: macronix: Add Octal 8D-8D-8D supports for Macronix mx25uw51245g Mason Yang
2020-05-28  7:58   ` Mason Yang
2020-05-28  8:26 ` [PATCH v3 00/14] mtd: spi-nor: add xSPI Octal DTR support Boris Brezillon
2020-05-28  8:26   ` Boris Brezillon
2020-05-29  5:27   ` masonccyang
2020-05-29  5:27     ` masonccyang

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