From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Chris Wilson" <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser
Date: Thu, 04 Jun 2020 11:36:28 -0000 [thread overview]
Message-ID: <159127058804.14555.941712483607278305@emeril.freedesktop.org> (raw)
In-Reply-To: <20200604103751.18816-1-chris@chris-wilson.co.uk>
== Series Details ==
Series: series starting with [01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser
URL : https://patchwork.freedesktop.org/series/77996/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
47e5bfbf30e3 drm/i915/gem: Mark the buffer pool as active for the cmdparser
7ec3c01e7a42 drm/i915: Trim set_timer_ms() intervals
00d105eacda7 drm/i915/gt: Set timeslicing priority from queue
7e77d0a206b9 drm/i915/gt: Always check to enable timeslicing if not submitting
b26c3cc35bd3 Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq"
fb7bb70a7283 drm/i915/gt: Couple tasklet scheduling for all CS interrupts
cba96e7cdecf drm/i915/gt: Support creation of 'internal' rings
ce8cae5ec931 drm/i915/gt: Use client timeline address for seqno writes
710e6262e4f4 drm/i915/gt: Infrastructure for ring scheduling
-:79: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#79:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 842 lines checked
f5112dc2ae3b drm/i915/gt: Enable busy-stats for ring-scheduler
-:13: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#13:
new file mode 100644
-:200: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#200: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:47:
+ udelay(100);
-:230: CHECK:USLEEP_RANGE: usleep_range is preferred over udelay; see Documentation/timers/timers-howto.rst
#230: FILE: drivers/gpu/drm/i915/gt/selftest_engine_pm.c:77:
+ udelay(100);
total: 0 errors, 1 warnings, 2 checks, 236 lines checked
d8fa9292586c drm/i915/gt: Track if an engine requires forcewake w/a
2cdc09a8fc16 drm/i915/gt: Implement ring scheduler for gen6/7
-:68: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#68: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:324:
+ *cs++ = i915_mmio_reg_offset(
-:70: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#70: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:326:
+ *cs++ = _MASKED_BIT_ENABLE(
-:105: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#105: FILE: drivers/gpu/drm/i915/gt/intel_ring_scheduler.c:361:
+ *cs++ = _MASKED_BIT_DISABLE(
total: 0 errors, 0 warnings, 3 checks, 506 lines checked
2ff1bb716df2 drm/i915/gt: Enable ring scheduling for gen6/7
cfed75109fb2 drm/i915/gem: Async GPU relocations only
dd90a9050b61 drm/i915: Add list_for_each_entry_safe_continue_reverse
-:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pos' - possible side-effects?
#20: FILE: drivers/gpu/drm/i915/i915_utils.h:269:
+#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \
+ for (pos = list_prev_entry(pos, member), \
+ n = list_prev_entry(pos, member); \
+ &pos->member != (head); \
+ pos = n, n = list_prev_entry(n, member))
-:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'n' - possible side-effects?
#20: FILE: drivers/gpu/drm/i915/i915_utils.h:269:
+#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \
+ for (pos = list_prev_entry(pos, member), \
+ n = list_prev_entry(pos, member); \
+ &pos->member != (head); \
+ pos = n, n = list_prev_entry(n, member))
-:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'member' - possible side-effects?
#20: FILE: drivers/gpu/drm/i915/i915_utils.h:269:
+#define list_for_each_entry_safe_continue_reverse(pos, n, head, member) \
+ for (pos = list_prev_entry(pos, member), \
+ n = list_prev_entry(pos, member); \
+ &pos->member != (head); \
+ pos = n, n = list_prev_entry(n, member))
total: 0 errors, 0 warnings, 3 checks, 12 lines checked
a5768b96efc5 drm/i915/gem: Separate reloc validation into an earlier step
-:101: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#101: FILE: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c:1408:
+ return (int)offset;
+ } else {
total: 0 errors, 1 warnings, 0 checks, 217 lines checked
37ab424926eb drm/i915/gem: Lift GPU relocation allocation
38ad7f8804a1 drm/i915/gem: Build the reloc request first
7cb671e36bbd drm/i915/gem: Add all GPU reloc awaits/signals en masse
1f32dc179ff3 dma-buf: Proxy fence, an unsignaled fence placeholder
-:45: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#45:
new file mode 100644
-:438: CHECK:UNCOMMENTED_DEFINITION: spinlock_t definition without comment
#438: FILE: drivers/dma-buf/st-dma-fence-proxy.c:20:
+ spinlock_t lock;
total: 0 errors, 1 warnings, 1 checks, 1158 lines checked
e665d3e71c75 drm/i915: Unpeel awaits on a proxy fence
f155632b03ef drm/i915/gem: Make relocations atomic within execbuf
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next prev parent reply other threads:[~2020-06-04 11:36 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-04 10:37 [Intel-gfx] [PATCH 01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 02/22] drm/i915: Trim set_timer_ms() intervals Chris Wilson
2020-06-04 12:54 ` Matthew Auld
2020-06-04 10:37 ` [Intel-gfx] [PATCH 03/22] drm/i915/gt: Set timeslicing priority from queue Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 04/22] drm/i915/gt: Always check to enable timeslicing if not submitting Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 05/22] Restore "drm/i915: drop engine_pin/unpin_breadcrumbs_irq" Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 06/22] drm/i915/gt: Couple tasklet scheduling for all CS interrupts Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 07/22] drm/i915/gt: Support creation of 'internal' rings Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 08/22] drm/i915/gt: Use client timeline address for seqno writes Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 09/22] drm/i915/gt: Infrastructure for ring scheduling Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 10/22] drm/i915/gt: Enable busy-stats for ring-scheduler Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 11/22] drm/i915/gt: Track if an engine requires forcewake w/a Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 12/22] drm/i915/gt: Implement ring scheduler for gen6/7 Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 13/22] drm/i915/gt: Enable ring scheduling " Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 14/22] drm/i915/gem: Async GPU relocations only Chris Wilson
2020-06-04 13:37 ` Matthew Auld
2020-06-04 13:44 ` Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 15/22] drm/i915: Add list_for_each_entry_safe_continue_reverse Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 16/22] drm/i915/gem: Separate reloc validation into an earlier step Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 17/22] drm/i915/gem: Lift GPU relocation allocation Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 18/22] drm/i915/gem: Build the reloc request first Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 19/22] drm/i915/gem: Add all GPU reloc awaits/signals en masse Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 20/22] dma-buf: Proxy fence, an unsignaled fence placeholder Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 21/22] drm/i915: Unpeel awaits on a proxy fence Chris Wilson
2020-06-04 10:37 ` [Intel-gfx] [PATCH 22/22] drm/i915/gem: Make relocations atomic within execbuf Chris Wilson
2020-06-04 11:36 ` Patchwork [this message]
2020-06-04 11:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/22] drm/i915/gem: Mark the buffer pool as active for the cmdparser Patchwork
2020-06-04 12:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-06-04 12:49 ` [Intel-gfx] [PATCH 01/22] " Matthew Auld
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