From: Marc Zyngier <maz@kernel.org>
To: Jason Cooper <jason@lakedaemon.net>,
Alexandre Torgue <alexandre.torgue@st.com>,
Thomas Gleixner <tglx@linutronix.de>,
Zenghui Yu <yuzenghui@huawei.com>,
linux-kernel@vger.kernel.org
Cc: linux-gpio@vger.kernel.org, marex@denx.de,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, stable@vger.kernel.org,
wanghaibin.wang@huawei.com
Subject: Re: [PATCH v2] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR
Date: Sat, 25 Jul 2020 15:23:35 +0100 [thread overview]
Message-ID: <159568680935.564881.3670480595242978406.b4-ty@kernel.org> (raw)
In-Reply-To: <20200720092328.708-1-yuzenghui@huawei.com>
On Mon, 20 Jul 2020 17:23:28 +0800, Zenghui Yu wrote:
> The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a
> register-based invalidation operation for a vPEID not mapped to that RD,
> or another RD within the same CommonLPIAff group.
>
> To follow this rule, commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual
> exclusion between vPE affinity change and RD access") tried to address the
> race between the RD accesses and the vPE affinity change, but somehow
> forgot to take GICR_INVALLR into account. Let's take the vpe_lock before
> evaluating vpe->col_idx to fix it.
Applied to irq/irqchip-5.9, thanks!
[1/1] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR
commit: fdccf1d9d10395abfe082f50694f374997c6e101
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Jason Cooper <jason@lakedaemon.net>,
Alexandre Torgue <alexandre.torgue@st.com>,
Thomas Gleixner <tglx@linutronix.de>,
Zenghui Yu <yuzenghui@huawei.com>,
linux-kernel@vger.kernel.org
Cc: marex@denx.de, stable@vger.kernel.org,
linux-gpio@vger.kernel.org, wanghaibin.wang@huawei.com,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR
Date: Sat, 25 Jul 2020 15:23:35 +0100 [thread overview]
Message-ID: <159568680935.564881.3670480595242978406.b4-ty@kernel.org> (raw)
In-Reply-To: <20200720092328.708-1-yuzenghui@huawei.com>
On Mon, 20 Jul 2020 17:23:28 +0800, Zenghui Yu wrote:
> The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a
> register-based invalidation operation for a vPEID not mapped to that RD,
> or another RD within the same CommonLPIAff group.
>
> To follow this rule, commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual
> exclusion between vPE affinity change and RD access") tried to address the
> race between the RD accesses and the vPE affinity change, but somehow
> forgot to take GICR_INVALLR into account. Let's take the vpe_lock before
> evaluating vpe->col_idx to fix it.
Applied to irq/irqchip-5.9, thanks!
[1/1] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR
commit: fdccf1d9d10395abfe082f50694f374997c6e101
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2020-07-25 14:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-20 9:23 [PATCH v2] irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLR Zenghui Yu
2020-07-25 14:23 ` Marc Zyngier [this message]
2020-07-25 14:23 ` Marc Zyngier
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