From: Stephen Boyd <sboyd@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>, Vinod Koul <vkoul@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Jeykumar Sankaran <jsanka@codeaurora.org>,
Chandan Uddaraju <chandanu@codeaurora.org>,
Vara Reddy <varar@codeaurora.org>,
Tanmay Shah <tanmay@codeaurora.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Manu Gautam <mgautam@codeaurora.org>,
Sandeep Maheswaram <sanm@codeaurora.org>,
Douglas Anderson <dianders@chromium.org>,
Sean Paul <seanpaul@chromium.org>,
Stephen Boyd <swboyd@chromium.org>,
Jonathan Marek <jonathan@marek.ca>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Rob Clark <robdclark@chromium.org>
Subject: Re: [PATCH v4 09/10] clk: qcom: dispcc: Update DP clk ops for phy design
Date: Tue, 22 Sep 2020 11:51:43 -0700 [thread overview]
Message-ID: <160080070307.310579.1550032345045011322@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20200916231202.3637932-10-swboyd@chromium.org>
Quoting Stephen Boyd (2020-09-16 16:12:01)
> The clk_rcg2_dp_determine_rate() function is used for the DP pixel clk.
> This function should return the rate that can be achieved by the pixel
> clk in 'struct clk_rate_request::rate' and match the logic similar to
> what is seen in clk_rcg2_dp_set_rate(). But that isn't the case. Instead
> the code merely bubbles the rate request up to the parent of the pixel
> clk and doesn't try to do a rational approximation of the rate that
> would be achieved by picking some m/n value for the RCG.
>
> Let's change this logic so that we can assume the parent clk frequency
> is fixed (it is because it's the VCO of the DP PLL that is configured
> based on the link rate) and so that we can calculate what the m/n value
> will be and adjust the req->rate appropriately.
>
> Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
> Cc: Chandan Uddaraju <chandanu@codeaurora.org>
> Cc: Vara Reddy <varar@codeaurora.org>
> Cc: Tanmay Shah <tanmay@codeaurora.org>
> Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> Cc: Manu Gautam <mgautam@codeaurora.org>
> Cc: Sandeep Maheswaram <sanm@codeaurora.org>
> Cc: Douglas Anderson <dianders@chromium.org>
> Cc: Sean Paul <seanpaul@chromium.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Jonathan Marek <jonathan@marek.ca>
> Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Cc: Rob Clark <robdclark@chromium.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> ---
Applied to clk-next
next prev parent reply other threads:[~2020-09-22 18:51 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 23:11 [PATCH v4 00/10] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 01/10] dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information Stephen Boyd
2020-09-23 16:01 ` Rob Herring
2020-09-16 23:11 ` [PATCH v4 02/10] phy: qcom-qmp: Move phy mode into struct qmp_phy Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 03/10] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 04/10] phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 05/10] phy: qcom-qmp: Get dp_com I/O resource by index Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 06/10] phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 07/10] phy: qcom-qmp: Add support for DP in USB3+DP combo phy Stephen Boyd
2020-09-16 23:12 ` [PATCH v4 08/10] phy: qcom-qmp: Add support for sc7180 DP phy Stephen Boyd
2020-09-16 23:12 ` [PATCH v4 09/10] clk: qcom: dispcc: Update DP clk ops for phy design Stephen Boyd
2020-09-22 18:51 ` Stephen Boyd [this message]
2020-09-16 23:12 ` [PATCH v4 10/10] drm/msm/dp: Use qmp phy for DP PLL and PHY Stephen Boyd
2020-09-28 5:58 ` [PATCH v4 00/10] Support qcom USB3+DP combo phy (or type-c phy) Vinod Koul
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