From: Vinod Koul <vkoul@kernel.org>
To: Stephen Boyd <swboyd@chromium.org>
Cc: Kishon Vijay Abraham I <kishon@ti.com>,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
Jeykumar Sankaran <jsanka@codeaurora.org>,
Chandan Uddaraju <chandanu@codeaurora.org>,
Vara Reddy <varar@codeaurora.org>,
Tanmay Shah <tanmay@codeaurora.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Manu Gautam <mgautam@codeaurora.org>,
Sandeep Maheswaram <sanm@codeaurora.org>,
Douglas Anderson <dianders@chromium.org>,
Sean Paul <seanpaul@chromium.org>,
Rob Clark <robdclark@chromium.org>,
Jonathan Marek <jonathan@marek.ca>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Stephen Boyd <sboyd@kernel.org>
Subject: Re: [PATCH v4 00/10] Support qcom USB3+DP combo phy (or type-c phy)
Date: Mon, 28 Sep 2020 11:28:19 +0530 [thread overview]
Message-ID: <20200928055819.GK2968@vkoul-mobl> (raw)
In-Reply-To: <20200916231202.3637932-1-swboyd@chromium.org>
On 16-09-20, 16:11, Stephen Boyd wrote:
> This patch series is based on v12 of the msm DP driver submission[1]
> plus a compliance patch[2]. In the v5 patch series review I suggested
> that the DP PHY and PLL be split out of the drm driver and moved to the
> qmp phy driver. This patch series does that, but it is still marked as
> an RFC because there are a couple more things to do, mostly updating the
> DT binding and getting agreement on how to structure the code.
>
> Eventually I believe the qmp phy driver will need to listen for type-c
> notifiers or somehow know the type-c pinout being used so this driver
> can program things slightly differently. Right now, I don't have any way
> to test it though, so I've left it as future work. For some more
> details, the DP phy and the USB3 phy share the same physical pins on the
> SoC and those pins pretty much line up with a type-c pinout modulo some
> CC pins for cable orientation detection logic that lives on the PMIC. So
> the DP phy can use all four lanes or it can use two lanes and the USB3
> phy can use two lanes. In the hardware designs that I have access to it
> is always two lanes for USB3 and two lanes for DP going through what
> looks like a type-c pinout so this just hard codes that configuration in
> the driver.
Applied 1 thru 8, thanks
--
~Vinod
prev parent reply other threads:[~2020-09-28 5:58 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 23:11 [PATCH v4 00/10] Support qcom USB3+DP combo phy (or type-c phy) Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 01/10] dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy information Stephen Boyd
2020-09-23 16:01 ` Rob Herring
2020-09-16 23:11 ` [PATCH v4 02/10] phy: qcom-qmp: Move phy mode into struct qmp_phy Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 03/10] phy: qcom-qmp: Remove 'initialized' in favor of 'init_count' Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 04/10] phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 05/10] phy: qcom-qmp: Get dp_com I/O resource by index Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 06/10] phy: qcom-qmp: Use devm_platform_ioremap_resource() to simplify Stephen Boyd
2020-09-16 23:11 ` [PATCH v4 07/10] phy: qcom-qmp: Add support for DP in USB3+DP combo phy Stephen Boyd
2020-09-16 23:12 ` [PATCH v4 08/10] phy: qcom-qmp: Add support for sc7180 DP phy Stephen Boyd
2020-09-16 23:12 ` [PATCH v4 09/10] clk: qcom: dispcc: Update DP clk ops for phy design Stephen Boyd
2020-09-22 18:51 ` Stephen Boyd
2020-09-16 23:12 ` [PATCH v4 10/10] drm/msm/dp: Use qmp phy for DP PLL and PHY Stephen Boyd
2020-09-28 5:58 ` Vinod Koul [this message]
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