From: Sagar Kadam <sagar.kadam@sifive.com> To: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, lee.jones@linaro.org, aou@eecs.berkeley.edu, yash.shah@sifive.com, Sagar Kadam <sagar.kadam@sifive.com> Subject: [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Date: Tue, 29 Sep 2020 21:02:09 +0530 [thread overview] Message-ID: <1601393531-2402-2-git-send-email-sagar.kadam@sifive.com> (raw) In-Reply-To: <1601393531-2402-1-git-send-email-sagar.kadam@sifive.com> FU540-C000 SoC from SiFive has a PRCI block, here we convert the device tree bindings from txt to YAML. Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com> --- .../bindings/clock/sifive/fu540-prci.txt | 46 ----------------- .../bindings/clock/sifive/fu540-prci.yaml | 60 ++++++++++++++++++++++ 2 files changed, 60 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt deleted file mode 100644 index 349808f..0000000 --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt +++ /dev/null @@ -1,46 +0,0 @@ -SiFive FU540 PRCI bindings - -On the FU540 family of SoCs, most system-wide clock and reset integration -is via the PRCI IP block. - -Required properties: -- compatible: Should be "sifive,<chip>-prci". Only one value is - supported: "sifive,fu540-c000-prci" -- reg: Should describe the PRCI's register target physical address region -- clocks: Should point to the hfclk device tree node and the rtcclk - device tree node. The RTC clock here is not a time-of-day clock, - but is instead a high-stability clock source for system timers - and cycle counters. -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock via the clock ID -macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. -These macros begin with PRCI_CLK_. - -The hfclk and rtcclk nodes are required, and represent physical -crystals or resonators located on the PCB. These nodes should be present -underneath /, rather than /soc. - -Examples: - -/* under /, in PCB-specific DT data */ -hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; -}; -rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - clock-output-names = "rtcclk"; -}; - -/* under /soc, in SoC-specific DT data */ -prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml new file mode 100644 index 0000000..c3be1b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) + +maintainers: + - Sagar Kadam <sagar.kadam@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +description: + On the FU540 family of SoCs, most system-wide clock and reset integration + is via the PRCI IP block. + The clock consumer should specify the desired clock via the clock ID + macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. + These macros begin with PRCI_CLK_. + + The hfclk and rtcclk nodes are required, and represent physical + crystals or resonators located on the PCB. These nodes should be present + underneath /, rather than /soc. + +properties: + compatible: + const: sifive,fu540-c000-prci + + reg: + maxItems: 1 + + clocks: + items: + - description: high frequency clock. + - description: RTL clock. + + clock-names: + items: + - const: hfclk + - const: rtcclk + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x10000000 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Sagar Kadam <sagar.kadam@sifive.com> To: linux-clk@vger.kernel.org Cc: devicetree@vger.kernel.org, aou@eecs.berkeley.edu, jason@lakedaemon.net, linux-pwm@vger.kernel.org, sboyd@kernel.org, maz@kernel.org, mturquette@baylibre.com, u.kleine-koenig@pengutronix.de, linux-kernel@vger.kernel.org, yash.shah@sifive.com, robh+dt@kernel.org, palmer@dabbelt.com, Sagar Kadam <sagar.kadam@sifive.com>, paul.walmsley@sifive.com, thierry.reding@gmail.com, linux-riscv@lists.infradead.org, lee.jones@linaro.org, tglx@linutronix.de Subject: [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Date: Tue, 29 Sep 2020 21:02:09 +0530 [thread overview] Message-ID: <1601393531-2402-2-git-send-email-sagar.kadam@sifive.com> (raw) In-Reply-To: <1601393531-2402-1-git-send-email-sagar.kadam@sifive.com> FU540-C000 SoC from SiFive has a PRCI block, here we convert the device tree bindings from txt to YAML. Signed-off-by: Sagar Kadam <sagar.kadam@sifive.com> --- .../bindings/clock/sifive/fu540-prci.txt | 46 ----------------- .../bindings/clock/sifive/fu540-prci.yaml | 60 ++++++++++++++++++++++ 2 files changed, 60 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt create mode 100644 Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt deleted file mode 100644 index 349808f..0000000 --- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.txt +++ /dev/null @@ -1,46 +0,0 @@ -SiFive FU540 PRCI bindings - -On the FU540 family of SoCs, most system-wide clock and reset integration -is via the PRCI IP block. - -Required properties: -- compatible: Should be "sifive,<chip>-prci". Only one value is - supported: "sifive,fu540-c000-prci" -- reg: Should describe the PRCI's register target physical address region -- clocks: Should point to the hfclk device tree node and the rtcclk - device tree node. The RTC clock here is not a time-of-day clock, - but is instead a high-stability clock source for system timers - and cycle counters. -- #clock-cells: Should be <1> - -The clock consumer should specify the desired clock via the clock ID -macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. -These macros begin with PRCI_CLK_. - -The hfclk and rtcclk nodes are required, and represent physical -crystals or resonators located on the PCB. These nodes should be present -underneath /, rather than /soc. - -Examples: - -/* under /, in PCB-specific DT data */ -hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; -}; -rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - clock-output-names = "rtcclk"; -}; - -/* under /soc, in SoC-specific DT data */ -prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml new file mode 100644 index 0000000..c3be1b6 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 SiFive, Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI) + +maintainers: + - Sagar Kadam <sagar.kadam@sifive.com> + - Paul Walmsley <paul.walmsley@sifive.com> + +description: + On the FU540 family of SoCs, most system-wide clock and reset integration + is via the PRCI IP block. + The clock consumer should specify the desired clock via the clock ID + macros defined in include/dt-bindings/clock/sifive-fu540-prci.h. + These macros begin with PRCI_CLK_. + + The hfclk and rtcclk nodes are required, and represent physical + crystals or resonators located on the PCB. These nodes should be present + underneath /, rather than /soc. + +properties: + compatible: + const: sifive,fu540-c000-prci + + reg: + maxItems: 1 + + clocks: + items: + - description: high frequency clock. + - description: RTL clock. + + clock-names: + items: + - const: hfclk + - const: rtcclk + + "#clock-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - "#clock-cells" + +additionalProperties: false + +examples: + - | + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x10000000 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; -- 2.7.4 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2020-09-29 15:33 UTC|newest] Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-29 15:32 [PATCH v2 0/3] convert sifive's prci, plic and pwm bindings to yaml Sagar Kadam 2020-09-29 15:32 ` Sagar Kadam 2020-09-29 15:32 ` Sagar Kadam [this message] 2020-09-29 15:32 ` [PATCH v2 1/3] dt-bindings: fu540: prci: convert PRCI bindings to json-schema Sagar Kadam 2020-10-06 18:42 ` Rob Herring 2020-10-06 18:42 ` Rob Herring 2020-10-07 3:38 ` Sagar Kadam 2020-10-07 3:38 ` Sagar Kadam 2020-09-29 15:32 ` [PATCH v2 2/3] dt-bindings: riscv: convert plic " Sagar Kadam 2020-09-29 15:32 ` Sagar Kadam 2020-10-06 18:44 ` Rob Herring 2020-10-06 18:44 ` Rob Herring 2020-09-29 15:32 ` [PATCH v2 3/3] dt-bindings: riscv: convert pwm " Sagar Kadam 2020-09-29 15:32 ` Sagar Kadam 2020-10-06 18:45 ` Rob Herring 2020-10-06 18:45 ` Rob Herring
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