From: Praveenkumar I <ipkumar@codeaurora.org> To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, sivaprak@codeaurora.org, peter.ujfalusi@ti.com, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: stable@vger.kernel.org, kathirav@codeaurora.org, Praveenkumar I <ipkumar@codeaurora.org> Subject: [PATCH] mtd: rawnand: qcom: Fix DMA sync on FLASH_STATUS register read Date: Fri, 9 Oct 2020 13:37:52 +0530 [thread overview] Message-ID: <1602230872-25616-1-git-send-email-ipkumar@codeaurora.org> (raw) After each codeword NAND_FLASH_STATUS is read for possible operational failures. But there is no DMA sync for CPU operation before reading it and this leads to incorrect or older copy of DMA buffer in reg_read_buf. This patch adds the DMA sync on reg_read_buf for CPU before reading it. Fixes: 5bc36b2bf6e2 ("mtd: rawnand: qcom: check for operation errors in case of raw read") Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org> --- drivers/mtd/nand/raw/qcom_nandc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index bd7a7251429b..5bb85f1ba84c 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1570,6 +1570,8 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt) struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); int i; + nandc_read_buffer_sync(nandc, true); + for (i = 0; i < cw_cnt; i++) { u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
WARNING: multiple messages have this Message-ID (diff)
From: Praveenkumar I <ipkumar@codeaurora.org> To: miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, sivaprak@codeaurora.org, peter.ujfalusi@ti.com, boris.brezillon@collabora.com, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org Cc: kathirav@codeaurora.org, Praveenkumar I <ipkumar@codeaurora.org>, stable@vger.kernel.org Subject: [PATCH] mtd: rawnand: qcom: Fix DMA sync on FLASH_STATUS register read Date: Fri, 9 Oct 2020 13:37:52 +0530 [thread overview] Message-ID: <1602230872-25616-1-git-send-email-ipkumar@codeaurora.org> (raw) After each codeword NAND_FLASH_STATUS is read for possible operational failures. But there is no DMA sync for CPU operation before reading it and this leads to incorrect or older copy of DMA buffer in reg_read_buf. This patch adds the DMA sync on reg_read_buf for CPU before reading it. Fixes: 5bc36b2bf6e2 ("mtd: rawnand: qcom: check for operation errors in case of raw read") Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org> --- drivers/mtd/nand/raw/qcom_nandc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c index bd7a7251429b..5bb85f1ba84c 100644 --- a/drivers/mtd/nand/raw/qcom_nandc.c +++ b/drivers/mtd/nand/raw/qcom_nandc.c @@ -1570,6 +1570,8 @@ static int check_flash_errors(struct qcom_nand_host *host, int cw_cnt) struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); int i; + nandc_read_buffer_sync(nandc, true); + for (i = 0; i < cw_cnt; i++) { u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next reply other threads:[~2020-10-09 8:08 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-10-09 8:07 Praveenkumar I [this message] 2020-10-09 8:07 ` [PATCH] mtd: rawnand: qcom: Fix DMA sync on FLASH_STATUS register read Praveenkumar I 2020-10-28 10:08 ` Miquel Raynal 2020-10-28 10:08 ` Miquel Raynal [not found] ` <24a781a3-488c-b638-1b92-0f279807446f@codeaurora.org> 2020-10-28 14:23 ` Miquel Raynal 2020-10-28 14:23 ` Miquel Raynal 2020-10-30 17:27 ` Miquel Raynal 2020-10-30 17:27 ` Miquel Raynal
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