From: Daoyuan Huang <daoyuan.huang@mediatek.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>,
Jernej Skrabec <jernej.skrabec@siol.net>
Cc: Maoguang Meng <maoguang.meng@mediatek.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
daoyuan huang <daoyuan.huang@mediatek.com>,
Ping-Hsun Wu <ping-hsun.wu@mediatek.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Rob Landley <rob@landley.net>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
<linux-media@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <tfiga@chromium.org>,
<drinkcat@chromium.org>, <acourbot@chromium.org>,
<pihsun@chromium.org>, <menghui.lin@mediatek.com>,
<sj.huang@mediatek.com>, <ben.lok@mediatek.com>,
<randy.wu@mediatek.com>, <moudy.ho@mediatek.com>,
<srv_heupstream@mediatek.com>
Subject: [PATCH v4 2/4] dts: arm64: mt8183: Add Mediatek MDP3 nodes
Date: Fri, 20 Nov 2020 10:29:04 +0800 [thread overview]
Message-ID: <1605839346-10648-3-git-send-email-daoyuan.huang@mediatek.com> (raw)
In-Reply-To: <1605839346-10648-1-git-send-email-daoyuan.huang@mediatek.com>
From: daoyuan huang <daoyuan.huang@mediatek.com>
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
---
Depend on:
[1] https://lore.kernel.org/patchwork/patch/1164746/
[2] https://patchwork.kernel.org/patch/11703299/
[3] https://patchwork.kernel.org/patch/11283773/
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 116 +++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 8fed72bb35d7..fdd809883ce7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/mt8183-clk.h>
+#include <dt-bindings/gce/mt8183-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
@@ -712,13 +713,128 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
+ mdp-comps = "mediatek,mt8183-mdp-dl",
+ "mediatek,mt8183-mdp-dl";
+ mdp-comp-ids = <0 1>;
reg = <0 0x14000000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
+ clocks = <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ };
+
+ mdp_rdma0: mdp-rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp-rdma",
+ "mediatek,mt8183-mdp3";
+ mediatek,scp = <&scp>;
+ mediatek,mdp-id = <0>;
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,imgsys = <&imgsys>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ1_SOF>,
+ <CMDQ_EVENT_MDP_TDSHP_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>,
+ <CMDQ_EVENT_MDP_WDMA0_SOF>,
+ <CMDQ_EVENT_MDP_WDMA0_EOF>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+ <CMDQ_EVENT_WPE_A_DONE>,
+ <CMDQ_EVENT_SPE_B_DONE>;
+ };
+
+ mdp_rsz0: mdp-rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp-rsz";
+ mediatek,mdp-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp_rsz1: mdp-rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp-rsz";
+ mediatek,mdp-id = <1>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
+
+ mdp_wrot0: mdp-wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp-wrot";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-path";
+ mdp-comp-ids = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_wdma: mdp-wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp-wdma";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-path";
+ mdp-comp-ids = <1>;
+ reg = <0 0x14006000 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_ccorr: mdp-ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp-ccorr";
+ mediatek,mdp-id = <0>;
+ reg = <0 0x1401c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
};
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-imgi",
+ "mediatek,mt8183-mdp-exto";
+ mdp-comp-ids = <0 1>;
reg = <0 0x15020000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1502XXXX 0 0x1000>;
#clock-cells = <1>;
};
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Daoyuan Huang <daoyuan.huang@mediatek.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>,
Jernej Skrabec <jernej.skrabec@siol.net>
Cc: Maoguang Meng <maoguang.meng@mediatek.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
menghui.lin@mediatek.com,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
drinkcat@chromium.org, Krzysztof Kozlowski <krzk@kernel.org>,
Ping-Hsun Wu <ping-hsun.wu@mediatek.com>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
daoyuan huang <daoyuan.huang@mediatek.com>,
sj.huang@mediatek.com, linux-mediatek@lists.infradead.org,
pihsun@chromium.org, linux-arm-kernel@lists.infradead.org,
randy.wu@mediatek.com, srv_heupstream@mediatek.com,
acourbot@chromium.org, linux-kernel@vger.kernel.org,
tfiga@chromium.org, ben.lok@mediatek.com, moudy.ho@mediatek.com,
Rob Landley <rob@landley.net>
Subject: [PATCH v4 2/4] dts: arm64: mt8183: Add Mediatek MDP3 nodes
Date: Fri, 20 Nov 2020 10:29:04 +0800 [thread overview]
Message-ID: <1605839346-10648-3-git-send-email-daoyuan.huang@mediatek.com> (raw)
In-Reply-To: <1605839346-10648-1-git-send-email-daoyuan.huang@mediatek.com>
From: daoyuan huang <daoyuan.huang@mediatek.com>
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
---
Depend on:
[1] https://lore.kernel.org/patchwork/patch/1164746/
[2] https://patchwork.kernel.org/patch/11703299/
[3] https://patchwork.kernel.org/patch/11283773/
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 116 +++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 8fed72bb35d7..fdd809883ce7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/mt8183-clk.h>
+#include <dt-bindings/gce/mt8183-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
@@ -712,13 +713,128 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
+ mdp-comps = "mediatek,mt8183-mdp-dl",
+ "mediatek,mt8183-mdp-dl";
+ mdp-comp-ids = <0 1>;
reg = <0 0x14000000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
+ clocks = <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ };
+
+ mdp_rdma0: mdp-rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp-rdma",
+ "mediatek,mt8183-mdp3";
+ mediatek,scp = <&scp>;
+ mediatek,mdp-id = <0>;
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,imgsys = <&imgsys>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ1_SOF>,
+ <CMDQ_EVENT_MDP_TDSHP_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>,
+ <CMDQ_EVENT_MDP_WDMA0_SOF>,
+ <CMDQ_EVENT_MDP_WDMA0_EOF>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+ <CMDQ_EVENT_WPE_A_DONE>,
+ <CMDQ_EVENT_SPE_B_DONE>;
+ };
+
+ mdp_rsz0: mdp-rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp-rsz";
+ mediatek,mdp-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp_rsz1: mdp-rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp-rsz";
+ mediatek,mdp-id = <1>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
+
+ mdp_wrot0: mdp-wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp-wrot";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-path";
+ mdp-comp-ids = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_wdma: mdp-wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp-wdma";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-path";
+ mdp-comp-ids = <1>;
+ reg = <0 0x14006000 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_ccorr: mdp-ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp-ccorr";
+ mediatek,mdp-id = <0>;
+ reg = <0 0x1401c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
};
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-imgi",
+ "mediatek,mt8183-mdp-exto";
+ mdp-comp-ids = <0 1>;
reg = <0 0x15020000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1502XXXX 0 0x1000>;
#clock-cells = <1>;
};
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
WARNING: multiple messages have this Message-ID (diff)
From: Daoyuan Huang <daoyuan.huang@mediatek.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Hans Verkuil <hverkuil-cisco@xs4all.nl>,
Jernej Skrabec <jernej.skrabec@siol.net>
Cc: Maoguang Meng <maoguang.meng@mediatek.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
menghui.lin@mediatek.com,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
drinkcat@chromium.org, Krzysztof Kozlowski <krzk@kernel.org>,
Ping-Hsun Wu <ping-hsun.wu@mediatek.com>,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
daoyuan huang <daoyuan.huang@mediatek.com>,
sj.huang@mediatek.com, linux-mediatek@lists.infradead.org,
pihsun@chromium.org, linux-arm-kernel@lists.infradead.org,
randy.wu@mediatek.com, srv_heupstream@mediatek.com,
acourbot@chromium.org, linux-kernel@vger.kernel.org,
tfiga@chromium.org, ben.lok@mediatek.com, moudy.ho@mediatek.com,
Rob Landley <rob@landley.net>
Subject: [PATCH v4 2/4] dts: arm64: mt8183: Add Mediatek MDP3 nodes
Date: Fri, 20 Nov 2020 10:29:04 +0800 [thread overview]
Message-ID: <1605839346-10648-3-git-send-email-daoyuan.huang@mediatek.com> (raw)
In-Reply-To: <1605839346-10648-1-git-send-email-daoyuan.huang@mediatek.com>
From: daoyuan huang <daoyuan.huang@mediatek.com>
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
---
Depend on:
[1] https://lore.kernel.org/patchwork/patch/1164746/
[2] https://patchwork.kernel.org/patch/11703299/
[3] https://patchwork.kernel.org/patch/11283773/
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 116 +++++++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 8fed72bb35d7..fdd809883ce7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/mt8183-clk.h>
+#include <dt-bindings/gce/mt8183-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/reset-controller/mt8183-resets.h>
@@ -712,13 +713,128 @@
mmsys: syscon@14000000 {
compatible = "mediatek,mt8183-mmsys", "syscon";
+ mdp-comps = "mediatek,mt8183-mdp-dl",
+ "mediatek,mt8183-mdp-dl";
+ mdp-comp-ids = <0 1>;
reg = <0 0x14000000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
+ clocks = <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ };
+
+ mdp_rdma0: mdp-rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp-rdma",
+ "mediatek,mt8183-mdp3";
+ mediatek,scp = <&scp>;
+ mediatek,mdp-id = <0>;
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,imgsys = <&imgsys>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ1_SOF>,
+ <CMDQ_EVENT_MDP_TDSHP_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>,
+ <CMDQ_EVENT_MDP_WDMA0_SOF>,
+ <CMDQ_EVENT_MDP_WDMA0_EOF>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+ <CMDQ_EVENT_WPE_A_DONE>,
+ <CMDQ_EVENT_SPE_B_DONE>;
+ };
+
+ mdp_rsz0: mdp-rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp-rsz";
+ mediatek,mdp-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp_rsz1: mdp-rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp-rsz";
+ mediatek,mdp-id = <1>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
+
+ mdp_wrot0: mdp-wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp-wrot";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-path";
+ mdp-comp-ids = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_wdma: mdp-wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp-wdma";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-path";
+ mdp-comp-ids = <1>;
+ reg = <0 0x14006000 0 0x1000>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ mdp_ccorr: mdp-ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp-ccorr";
+ mediatek,mdp-id = <0>;
+ reg = <0 0x1401c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
};
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
+ mediatek,mdp-id = <0>;
+ mdp-comps = "mediatek,mt8183-mdp-imgi",
+ "mediatek,mt8183-mdp-exto";
+ mdp-comp-ids = <0 1>;
reg = <0 0x15020000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1502XXXX 0 0x1000>;
#clock-cells = <1>;
};
--
2.18.0
_______________________________________________
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next prev parent reply other threads:[~2020-11-20 2:34 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-20 2:29 [PATCH v4 0/4] media: mediatek: support mdp3 on mt8183 platform Daoyuan Huang
2020-11-20 2:29 ` Daoyuan Huang
2020-11-20 2:29 ` Daoyuan Huang
2020-11-20 2:29 ` [PATCH v4 1/4] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Daoyuan Huang
2020-11-20 2:29 ` Daoyuan Huang
2020-11-20 2:29 ` Daoyuan Huang
2020-11-20 14:41 ` Chun-Kuang Hu
2020-11-20 14:41 ` Chun-Kuang Hu
2020-11-20 14:41 ` Chun-Kuang Hu
2020-12-01 1:35 ` Rob Herring
2020-12-01 1:35 ` Rob Herring
2020-12-01 1:35 ` Rob Herring
2020-11-20 2:29 ` Daoyuan Huang [this message]
2020-11-20 2:29 ` [PATCH v4 2/4] dts: arm64: mt8183: Add Mediatek MDP3 nodes Daoyuan Huang
2020-11-20 2:29 ` Daoyuan Huang
2020-11-20 15:15 ` Fabien Parent
2020-11-20 15:15 ` Fabien Parent
2020-11-20 15:15 ` Fabien Parent
2020-11-20 2:29 ` [PATCH v4 3/4] media: platform: Add Mediatek MDP3 driver KConfig Daoyuan Huang
2020-11-20 2:29 ` Daoyuan Huang
2020-11-20 2:29 ` Daoyuan Huang
2020-11-20 2:29 ` [PATCH v4 4/4] media: platform: mtk-mdp3: Add Mediatek MDP3 driver Daoyuan Huang
2020-11-20 2:29 ` Daoyuan Huang
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