From: Jacob Pan <jacob.jun.pan@linux.intel.com> To: LKML <linux-kernel@vger.kernel.org>, iommu@lists.linux-foundation.org, Joerg Roedel <joro@8bytes.org>, "Lu Baolu" <baolu.lu@linux.intel.com>, David Woodhouse <dwmw2@infradead.org> Cc: Yi Liu <yi.l.liu@intel.com>, Raj Ashok <ashok.raj@intel.com>, "Tian, Kevin" <kevin.tian@intel.com>, Eric Auger <eric.auger@redhat.com>, Jean-Philippe Brucker <jean-philippe@linaro.com>, Jacob Pan <jacob.jun.pan@linux.intel.com>, Sanjay Kumar <sanjay.k.kumar@intel.com> Subject: [PATCH v2 1/4] iommu/vt-d: Enable write protect for supervisor SVM Date: Tue, 2 Mar 2021 02:13:57 -0800 [thread overview] Message-ID: <1614680040-1989-2-git-send-email-jacob.jun.pan@linux.intel.com> (raw) In-Reply-To: <1614680040-1989-1-git-send-email-jacob.jun.pan@linux.intel.com> Write protect bit, when set, inhibits supervisor writes to the read-only pages. In supervisor shared virtual addressing (SVA), where page tables are shared between CPU and DMA, IOMMU PASID entry WPE bit should match CR0.WP bit in the CPU. This patch sets WPE bit for supervisor PASIDs if CR0.WP is set. Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> --- drivers/iommu/intel/pasid.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 0cceaabc3ce6..0b7e0e726ade 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -410,6 +410,15 @@ static inline void pasid_set_sre(struct pasid_entry *pe) pasid_set_bits(&pe->val[2], 1 << 0, 1); } +/* + * Setup the WPE(Write Protect Enable) field (Bit 132) of a + * scalable mode PASID entry. + */ +static inline void pasid_set_wpe(struct pasid_entry *pe) +{ + pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4); +} + /* * Setup the P(Present) field (Bit 0) of a scalable mode PASID * entry. @@ -553,6 +562,20 @@ static void pasid_flush_caches(struct intel_iommu *iommu, } } +static inline int pasid_enable_wpe(struct pasid_entry *pte) +{ + unsigned long cr0 = read_cr0(); + + /* CR0.WP is normally set but just to be sure */ + if (unlikely(!(cr0 & X86_CR0_WP))) { + pr_err_ratelimited("No CPU write protect!\n"); + return -EINVAL; + } + pasid_set_wpe(pte); + + return 0; +}; + /* * Set up the scalable mode pasid table entry for first only * translation type. @@ -584,6 +607,9 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, return -EINVAL; } pasid_set_sre(pte); + if (pasid_enable_wpe(pte)) + return -EINVAL; + } if (flags & PASID_FLAG_FL5LP) { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Jacob Pan <jacob.jun.pan@linux.intel.com> To: LKML <linux-kernel@vger.kernel.org>, iommu@lists.linux-foundation.org, Joerg Roedel <joro@8bytes.org>, "Lu Baolu" <baolu.lu@linux.intel.com>, David Woodhouse <dwmw2@infradead.org> Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>, Sanjay Kumar <sanjay.k.kumar@intel.com>, Jean-Philippe Brucker <jean-philippe@linaro.com> Subject: [PATCH v2 1/4] iommu/vt-d: Enable write protect for supervisor SVM Date: Tue, 2 Mar 2021 02:13:57 -0800 [thread overview] Message-ID: <1614680040-1989-2-git-send-email-jacob.jun.pan@linux.intel.com> (raw) In-Reply-To: <1614680040-1989-1-git-send-email-jacob.jun.pan@linux.intel.com> Write protect bit, when set, inhibits supervisor writes to the read-only pages. In supervisor shared virtual addressing (SVA), where page tables are shared between CPU and DMA, IOMMU PASID entry WPE bit should match CR0.WP bit in the CPU. This patch sets WPE bit for supervisor PASIDs if CR0.WP is set. Signed-off-by: Sanjay Kumar <sanjay.k.kumar@intel.com> Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com> --- drivers/iommu/intel/pasid.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c index 0cceaabc3ce6..0b7e0e726ade 100644 --- a/drivers/iommu/intel/pasid.c +++ b/drivers/iommu/intel/pasid.c @@ -410,6 +410,15 @@ static inline void pasid_set_sre(struct pasid_entry *pe) pasid_set_bits(&pe->val[2], 1 << 0, 1); } +/* + * Setup the WPE(Write Protect Enable) field (Bit 132) of a + * scalable mode PASID entry. + */ +static inline void pasid_set_wpe(struct pasid_entry *pe) +{ + pasid_set_bits(&pe->val[2], 1 << 4, 1 << 4); +} + /* * Setup the P(Present) field (Bit 0) of a scalable mode PASID * entry. @@ -553,6 +562,20 @@ static void pasid_flush_caches(struct intel_iommu *iommu, } } +static inline int pasid_enable_wpe(struct pasid_entry *pte) +{ + unsigned long cr0 = read_cr0(); + + /* CR0.WP is normally set but just to be sure */ + if (unlikely(!(cr0 & X86_CR0_WP))) { + pr_err_ratelimited("No CPU write protect!\n"); + return -EINVAL; + } + pasid_set_wpe(pte); + + return 0; +}; + /* * Set up the scalable mode pasid table entry for first only * translation type. @@ -584,6 +607,9 @@ int intel_pasid_setup_first_level(struct intel_iommu *iommu, return -EINVAL; } pasid_set_sre(pte); + if (pasid_enable_wpe(pte)) + return -EINVAL; + } if (flags & PASID_FLAG_FL5LP) { -- 2.25.1 _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2021-03-02 21:50 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-03-02 10:13 [PATCH v2 0/4] Misc vSVA fixes for VT-d Jacob Pan 2021-03-02 10:13 ` Jacob Pan 2021-03-02 10:13 ` Jacob Pan [this message] 2021-03-02 10:13 ` [PATCH v2 1/4] iommu/vt-d: Enable write protect for supervisor SVM Jacob Pan 2021-03-03 4:56 ` Lu Baolu 2021-03-03 4:56 ` Lu Baolu 2021-03-22 17:53 ` Guenter Roeck 2021-03-22 17:53 ` Guenter Roeck 2021-03-30 17:52 ` Jacob Pan 2021-03-30 17:52 ` Jacob Pan 2021-03-30 19:02 ` Guenter Roeck 2021-03-30 19:02 ` Guenter Roeck 2021-03-02 10:13 ` [PATCH v2 2/4] iommu/vt-d: Enable write protect propagation from guest Jacob Pan 2021-03-02 10:13 ` Jacob Pan 2021-03-03 4:57 ` Lu Baolu 2021-03-03 4:57 ` Lu Baolu 2021-03-02 10:13 ` [PATCH v2 3/4] iommu/vt-d: Reject unsupported page request modes Jacob Pan 2021-03-02 10:13 ` Jacob Pan 2021-03-02 10:14 ` [PATCH v2 4/4] iommu/vt-d: Calculate and set flags for handle_mm_fault Jacob Pan 2021-03-02 10:14 ` Jacob Pan 2021-03-18 10:43 ` [PATCH v2 0/4] Misc vSVA fixes for VT-d Joerg Roedel 2021-03-18 10:43 ` Joerg Roedel
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1614680040-1989-2-git-send-email-jacob.jun.pan@linux.intel.com \ --to=jacob.jun.pan@linux.intel.com \ --cc=ashok.raj@intel.com \ --cc=baolu.lu@linux.intel.com \ --cc=dwmw2@infradead.org \ --cc=eric.auger@redhat.com \ --cc=iommu@lists.linux-foundation.org \ --cc=jean-philippe@linaro.com \ --cc=joro@8bytes.org \ --cc=kevin.tian@intel.com \ --cc=linux-kernel@vger.kernel.org \ --cc=sanjay.k.kumar@intel.com \ --cc=yi.l.liu@intel.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.