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From: Will Deacon <will@kernel.org>
To: Rich Wiley <rwiley@nvidia.com>, catalin.marinas@arm.com
Cc: kernel-team@android.com, Will Deacon <will@kernel.org>,
	linux-tegra@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2] arm64: kernel: disable CNP on Carmel
Date: Thu, 25 Mar 2021 11:19:04 +0000	[thread overview]
Message-ID: <161666594391.223463.996446144212506291.b4-ty@kernel.org> (raw)
In-Reply-To: <20210324002809.30271-1-rwiley@nvidia.com>

On Tue, 23 Mar 2021 17:28:09 -0700, Rich Wiley wrote:
> On NVIDIA Carmel cores, CNP behaves differently than it does on standard
> ARM cores. On Carmel, if two cores have CNP enabled and share an L2 TLB
> entry created by core0 for a specific ASID, a non-shareable TLBI from
> core1 may still see the shared entry. On standard ARM cores, that TLBI
> will invalidate the shared entry as well.
> 
> This causes issues with patchsets that attempt to do local TLBIs based
> on cpumasks instead of broadcast TLBIs. Avoid these issues by disabling
> CNP support for NVIDIA Carmel cores.

Applied to arm64 (for-next/fixes), thanks!

[1/1] arm64: kernel: disable CNP on Carmel
      https://git.kernel.org/arm64/c/20109a859a9b

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

WARNING: multiple messages have this Message-ID (diff)
From: Will Deacon <will@kernel.org>
To: Rich Wiley <rwiley@nvidia.com>, catalin.marinas@arm.com
Cc: kernel-team@android.com, Will Deacon <will@kernel.org>,
	linux-tegra@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH V2] arm64: kernel: disable CNP on Carmel
Date: Thu, 25 Mar 2021 11:19:04 +0000	[thread overview]
Message-ID: <161666594391.223463.996446144212506291.b4-ty@kernel.org> (raw)
In-Reply-To: <20210324002809.30271-1-rwiley@nvidia.com>

On Tue, 23 Mar 2021 17:28:09 -0700, Rich Wiley wrote:
> On NVIDIA Carmel cores, CNP behaves differently than it does on standard
> ARM cores. On Carmel, if two cores have CNP enabled and share an L2 TLB
> entry created by core0 for a specific ASID, a non-shareable TLBI from
> core1 may still see the shared entry. On standard ARM cores, that TLBI
> will invalidate the shared entry as well.
> 
> This causes issues with patchsets that attempt to do local TLBIs based
> on cpumasks instead of broadcast TLBIs. Avoid these issues by disabling
> CNP support for NVIDIA Carmel cores.

Applied to arm64 (for-next/fixes), thanks!

[1/1] arm64: kernel: disable CNP on Carmel
      https://git.kernel.org/arm64/c/20109a859a9b

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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  reply	other threads:[~2021-03-25 11:20 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-24  0:28 [PATCH V2] arm64: kernel: disable CNP on Carmel Rich Wiley
2021-03-24  0:28 ` Rich Wiley
2021-03-25 11:19 ` Will Deacon [this message]
2021-03-25 11:19   ` Will Deacon

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