From: guoren@kernel.org
To: guoren@kernel.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-csky@vger.kernel.org, linux-arch@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org,
openrisc@lists.librecores.org, sparclinux@vger.kernel.org,
Guo Ren <guoren@linux.alibaba.com>
Subject: [PATCH v5 0/7] riscv: Add qspinlock/qrwlock
Date: Sun, 28 Mar 2021 06:30:21 +0000 [thread overview]
Message-ID: <1616913028-83376-1-git-send-email-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
Current riscv is still using baby spinlock implementation. It'll cause
fairness and cache line bouncing problems. Many people are involved
and pay the efforts to improve it:
- The first version of patch was made in 2019.1:
https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/#r
- The second version was made in 2020.11:
https://lore.kernel.org/linux-riscv/1606225437-22948-2-git-send-email-guoren@kernel.org/
- A good discussion at Platform HSC.2021-03-08:
https://drive.google.com/drive/folders/1ooqdnIsYx7XKor5O1XTtM6D1CHp4hc0p
Hope your comments and Tested-by or Co-developed-by or Reviewed-by ...
Let's kick the qspinlock into riscv right now (Also for the
architecture which hasn't xchg16 atomic instruction.)
Change V5:
- Fixup #endif comment typo by Waiman
- Remove cmpxchg coding convention patches which will get into a
separate patchset later by Arnd's advice
- Try to involve more architectures in the discussion
Change V4:
- Remove custom sub-word xchg implementation
- Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock
Change V3:
- Coding convention by Peter Zijlstra's advices
Change V2:
- Coding convention in cmpxchg.h
- Re-implement short xchg
- Remove char & cmpxchg implementations
Guo Ren (6):
locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
sparc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Michael Clark (1):
riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
arch/csky/Kconfig | 2 +
arch/csky/include/asm/Kbuild | 2 +
arch/csky/include/asm/spinlock.h | 82 +--------------
arch/csky/include/asm/spinlock_types.h | 16 +--
arch/openrisc/Kconfig | 1 +
arch/powerpc/Kconfig | 1 +
arch/riscv/Kconfig | 3 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
arch/sparc/Kconfig | 1 +
arch/xtensa/Kconfig | 1 +
kernel/Kconfig.locks | 3 +
kernel/locking/qspinlock.c | 46 +++++----
14 files changed, 49 insertions(+), 253 deletions(-)
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-csky@vger.kernel.org, linux-arch@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org, linux-xtensa@linux-xtensa.org,
openrisc@lists.librecores.org, sparclinux@vger.kernel.org,
Guo Ren <guoren@linux.alibaba.com>
Subject: [PATCH v5 0/7] riscv: Add qspinlock/qrwlock
Date: Sun, 28 Mar 2021 06:30:21 +0000 [thread overview]
Message-ID: <1616913028-83376-1-git-send-email-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
Current riscv is still using baby spinlock implementation. It'll cause
fairness and cache line bouncing problems. Many people are involved
and pay the efforts to improve it:
- The first version of patch was made in 2019.1:
https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/#r
- The second version was made in 2020.11:
https://lore.kernel.org/linux-riscv/1606225437-22948-2-git-send-email-guoren@kernel.org/
- A good discussion at Platform HSC.2021-03-08:
https://drive.google.com/drive/folders/1ooqdnIsYx7XKor5O1XTtM6D1CHp4hc0p
Hope your comments and Tested-by or Co-developed-by or Reviewed-by ...
Let's kick the qspinlock into riscv right now (Also for the
architecture which hasn't xchg16 atomic instruction.)
Change V5:
- Fixup #endif comment typo by Waiman
- Remove cmpxchg coding convention patches which will get into a
separate patchset later by Arnd's advice
- Try to involve more architectures in the discussion
Change V4:
- Remove custom sub-word xchg implementation
- Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock
Change V3:
- Coding convention by Peter Zijlstra's advices
Change V2:
- Coding convention in cmpxchg.h
- Re-implement short xchg
- Remove char & cmpxchg implementations
Guo Ren (6):
locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
sparc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Michael Clark (1):
riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
arch/csky/Kconfig | 2 +
arch/csky/include/asm/Kbuild | 2 +
arch/csky/include/asm/spinlock.h | 82 +--------------
arch/csky/include/asm/spinlock_types.h | 16 +--
arch/openrisc/Kconfig | 1 +
arch/powerpc/Kconfig | 1 +
arch/riscv/Kconfig | 3 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
arch/sparc/Kconfig | 1 +
arch/xtensa/Kconfig | 1 +
kernel/Kconfig.locks | 3 +
kernel/locking/qspinlock.c | 46 +++++----
14 files changed, 49 insertions(+), 253 deletions(-)
--
2.17.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org
To: guoren@kernel.org
Cc: linux-arch@vger.kernel.org, linux-xtensa@linux-xtensa.org,
Guo Ren <guoren@linux.alibaba.com>,
linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org,
openrisc@lists.librecores.org, sparclinux@vger.kernel.org,
linux-riscv@lists.infradead.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v5 0/7] riscv: Add qspinlock/qrwlock
Date: Sun, 28 Mar 2021 06:30:21 +0000 [thread overview]
Message-ID: <1616913028-83376-1-git-send-email-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
Current riscv is still using baby spinlock implementation. It'll cause
fairness and cache line bouncing problems. Many people are involved
and pay the efforts to improve it:
- The first version of patch was made in 2019.1:
https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark@mac.com/#r
- The second version was made in 2020.11:
https://lore.kernel.org/linux-riscv/1606225437-22948-2-git-send-email-guoren@kernel.org/
- A good discussion at Platform HSC.2021-03-08:
https://drive.google.com/drive/folders/1ooqdnIsYx7XKor5O1XTtM6D1CHp4hc0p
Hope your comments and Tested-by or Co-developed-by or Reviewed-by ...
Let's kick the qspinlock into riscv right now (Also for the
architecture which hasn't xchg16 atomic instruction.)
Change V5:
- Fixup #endif comment typo by Waiman
- Remove cmpxchg coding convention patches which will get into a
separate patchset later by Arnd's advice
- Try to involve more architectures in the discussion
Change V4:
- Remove custom sub-word xchg implementation
- Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock
Change V3:
- Coding convention by Peter Zijlstra's advices
Change V2:
- Coding convention in cmpxchg.h
- Re-implement short xchg
- Remove char & cmpxchg implementations
Guo Ren (6):
locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
sparc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Michael Clark (1):
riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
arch/csky/Kconfig | 2 +
arch/csky/include/asm/Kbuild | 2 +
arch/csky/include/asm/spinlock.h | 82 +--------------
arch/csky/include/asm/spinlock_types.h | 16 +--
arch/openrisc/Kconfig | 1 +
arch/powerpc/Kconfig | 1 +
arch/riscv/Kconfig | 3 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
arch/sparc/Kconfig | 1 +
arch/xtensa/Kconfig | 1 +
kernel/Kconfig.locks | 3 +
kernel/locking/qspinlock.c | 46 +++++----
14 files changed, 49 insertions(+), 253 deletions(-)
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org <guoren@kernel.org>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v5 0/7] riscv: Add qspinlock/qrwlock
Date: Sun, 28 Mar 2021 06:30:21 +0000 [thread overview]
Message-ID: <1616913028-83376-1-git-send-email-guoren@kernel.org> (raw)
From: Guo Ren <guoren@linux.alibaba.com>
Current riscv is still using baby spinlock implementation. It'll cause
fairness and cache line bouncing problems. Many people are involved
and pay the efforts to improve it:
- The first version of patch was made in 2019.1:
https://lore.kernel.org/linux-riscv/20190211043829.30096-1-michaeljclark at mac.com/#r
- The second version was made in 2020.11:
https://lore.kernel.org/linux-riscv/1606225437-22948-2-git-send-email-guoren at kernel.org/
- A good discussion at Platform HSC.2021-03-08:
https://drive.google.com/drive/folders/1ooqdnIsYx7XKor5O1XTtM6D1CHp4hc0p
Hope your comments and Tested-by or Co-developed-by or Reviewed-by ...
Let's kick the qspinlock into riscv right now (Also for the
architecture which hasn't xchg16 atomic instruction.)
Change V5:
- Fixup #endif comment typo by Waiman
- Remove cmpxchg coding convention patches which will get into a
separate patchset later by Arnd's advice
- Try to involve more architectures in the discussion
Change V4:
- Remove custom sub-word xchg implementation
- Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 in locking/qspinlock
Change V3:
- Coding convention by Peter Zijlstra's advices
Change V2:
- Coding convention in cmpxchg.h
- Re-implement short xchg
- Remove char & cmpxchg implementations
Guo Ren (6):
locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
csky: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
openrisc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
sparc: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
xtensa: qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32
Michael Clark (1):
riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock
arch/csky/Kconfig | 2 +
arch/csky/include/asm/Kbuild | 2 +
arch/csky/include/asm/spinlock.h | 82 +--------------
arch/csky/include/asm/spinlock_types.h | 16 +--
arch/openrisc/Kconfig | 1 +
arch/powerpc/Kconfig | 1 +
arch/riscv/Kconfig | 3 +
arch/riscv/include/asm/Kbuild | 3 +
arch/riscv/include/asm/spinlock.h | 126 +-----------------------
arch/riscv/include/asm/spinlock_types.h | 15 +--
arch/sparc/Kconfig | 1 +
arch/xtensa/Kconfig | 1 +
kernel/Kconfig.locks | 3 +
kernel/locking/qspinlock.c | 46 +++++----
14 files changed, 49 insertions(+), 253 deletions(-)
--
2.17.1
next reply other threads:[~2021-03-28 6:31 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-28 6:30 guoren [this message]
2021-03-28 6:30 ` [OpenRISC] [PATCH v5 0/7] riscv: Add qspinlock/qrwlock guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` [PATCH v5 1/7] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-03-28 6:30 ` [OpenRISC] " guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` [PATCH v5 2/7] riscv: Convert custom spinlock/rwlock to generic qspinlock/qrwlock guoren
2021-03-28 6:30 ` [OpenRISC] " guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` [PATCH v5 3/7] csky: " guoren
2021-03-28 6:30 ` [OpenRISC] " guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` [PATCH v5 4/7] powerpc/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 guoren
2021-03-28 6:30 ` [OpenRISC] " guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` guoren
2021-03-28 11:14 ` Christophe Leroy
2021-03-28 11:14 ` [OpenRISC] " Christophe Leroy
2021-03-28 11:14 ` Christophe Leroy
2021-03-28 11:36 ` Guo Ren
2021-03-28 11:36 ` [OpenRISC] " Guo Ren
2021-03-28 11:36 ` Guo Ren
2021-03-28 6:30 ` [PATCH v5 5/7] openrisc: qspinlock: " guoren
2021-03-28 6:30 ` [OpenRISC] " guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` [PATCH v5 6/7] sparc: " guoren
2021-03-28 6:30 ` [OpenRISC] " guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` [PATCH v5 7/7] xtensa: " guoren
2021-03-28 6:30 ` [OpenRISC] " guoren
2021-03-28 6:30 ` guoren
2021-03-28 6:30 ` guoren
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