From: "Heiko Stübner" <heiko@sntech.de>
To: Lin Huang <hl@rock-chips.com>
Cc: mark.yao@rock-chips.com, myungjoo.ham@samsung.com,
cw00.choi@samsung.com, airlied@linux.ie, mturquette@baylibre.com,
dbasehore@chromium.org, sboyd@codeaurora.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
dianders@chromium.org, linux-rockchip@lists.infradead.org,
kyungmin.park@samsung.com, linux-arm-kernel@lists.infradead.org,
tixy@linaro.org, xsf@rock-chips.com, typ@rock-chips.com
Subject: Re: [PATCH v3 2/7] clk: rockchip: add new clock-type for the ddrclk
Date: Sun, 24 Jul 2016 11:09:02 +0200 [thread overview]
Message-ID: <1619904.zXvqDRdkgD@diego> (raw)
In-Reply-To: <1469178440-4668-3-git-send-email-hl@rock-chips.com>
Am Freitag, 22. Juli 2016, 17:07:15 schrieb Lin Huang:
> @@ -488,6 +496,25 @@ struct rockchip_clk_branch {
> .child = ch, \
> }
>
> +#define COMPOSITE_DDRC(_id, cname, pnames, f, mo, ms, mw, mf, \
> + ds, dw, df) \
> + { \
> + .id = _id, \
> + .branch_type = branch_ddrc, \
> + .name = cname, \
> + .parent_names = pnames, \
> + .num_parents = ARRAY_SIZE(pnames), \
> + .flags = f, \
> + .muxdiv_offset = mo, \
> + .mux_shift = ms, \
> + .mux_width = mw, \
> + .mux_flags = mf, \
> + .div_shift = ds, \
> + .div_width = dw, \
> + .div_flags = df, \
> + .gate_offset = -1, \
> + }
> +
the mux and div-flags are not used in your clock type. Instead I think we could
go a similar way as the inverter-type, having one flag type, which could for
example encode the interface type ROCKCHIP_DDRCLK_SIP, etc.
Because right now there exist 3 types on how to set the ddr clk, SIP, an SCPI-
variant and through code in SRAM (rk3288), while the core clock type on the
side of the CRU is pretty much the same.
And while it is definitly not necessary to do that now, I think the ddrclk-type
can hold the other interfaces as well in the future.
Heiko
WARNING: multiple messages have this Message-ID (diff)
From: "Heiko Stübner" <heiko@sntech.de>
To: Lin Huang <hl@rock-chips.com>
Cc: tixy@linaro.org, typ@rock-chips.com,
linux-rockchip@lists.infradead.org, mturquette@baylibre.com,
dbasehore@chromium.org, sboyd@codeaurora.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
dianders@chromium.org, xsf@rock-chips.com, cw00.choi@samsung.com,
kyungmin.park@samsung.com, myungjoo.ham@samsung.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 2/7] clk: rockchip: add new clock-type for the ddrclk
Date: Sun, 24 Jul 2016 11:09:02 +0200 [thread overview]
Message-ID: <1619904.zXvqDRdkgD@diego> (raw)
In-Reply-To: <1469178440-4668-3-git-send-email-hl@rock-chips.com>
Am Freitag, 22. Juli 2016, 17:07:15 schrieb Lin Huang:
> @@ -488,6 +496,25 @@ struct rockchip_clk_branch {
> .child = ch, \
> }
>
> +#define COMPOSITE_DDRC(_id, cname, pnames, f, mo, ms, mw, mf, \
> + ds, dw, df) \
> + { \
> + .id = _id, \
> + .branch_type = branch_ddrc, \
> + .name = cname, \
> + .parent_names = pnames, \
> + .num_parents = ARRAY_SIZE(pnames), \
> + .flags = f, \
> + .muxdiv_offset = mo, \
> + .mux_shift = ms, \
> + .mux_width = mw, \
> + .mux_flags = mf, \
> + .div_shift = ds, \
> + .div_width = dw, \
> + .div_flags = df, \
> + .gate_offset = -1, \
> + }
> +
the mux and div-flags are not used in your clock type. Instead I think we could
go a similar way as the inverter-type, having one flag type, which could for
example encode the interface type ROCKCHIP_DDRCLK_SIP, etc.
Because right now there exist 3 types on how to set the ddr clk, SIP, an SCPI-
variant and through code in SRAM (rk3288), while the core clock type on the
side of the CRU is pretty much the same.
And while it is definitly not necessary to do that now, I think the ddrclk-type
can hold the other interfaces as well in the future.
Heiko
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
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WARNING: multiple messages have this Message-ID (diff)
From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 2/7] clk: rockchip: add new clock-type for the ddrclk
Date: Sun, 24 Jul 2016 11:09:02 +0200 [thread overview]
Message-ID: <1619904.zXvqDRdkgD@diego> (raw)
In-Reply-To: <1469178440-4668-3-git-send-email-hl@rock-chips.com>
Am Freitag, 22. Juli 2016, 17:07:15 schrieb Lin Huang:
> @@ -488,6 +496,25 @@ struct rockchip_clk_branch {
> .child = ch, \
> }
>
> +#define COMPOSITE_DDRC(_id, cname, pnames, f, mo, ms, mw, mf, \
> + ds, dw, df) \
> + { \
> + .id = _id, \
> + .branch_type = branch_ddrc, \
> + .name = cname, \
> + .parent_names = pnames, \
> + .num_parents = ARRAY_SIZE(pnames), \
> + .flags = f, \
> + .muxdiv_offset = mo, \
> + .mux_shift = ms, \
> + .mux_width = mw, \
> + .mux_flags = mf, \
> + .div_shift = ds, \
> + .div_width = dw, \
> + .div_flags = df, \
> + .gate_offset = -1, \
> + }
> +
the mux and div-flags are not used in your clock type. Instead I think we could
go a similar way as the inverter-type, having one flag type, which could for
example encode the interface type ROCKCHIP_DDRCLK_SIP, etc.
Because right now there exist 3 types on how to set the ddr clk, SIP, an SCPI-
variant and through code in SRAM (rk3288), while the core clock type on the
side of the CRU is pretty much the same.
And while it is definitly not necessary to do that now, I think the ddrclk-type
can hold the other interfaces as well in the future.
Heiko
next prev parent reply other threads:[~2016-07-24 9:09 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-22 9:07 [PATCH v3 0/7] rk3399 support ddr frequency scaling Lin Huang
2016-07-22 9:07 ` Lin Huang
2016-07-22 9:07 ` [PATCH v3 1/7] firmware: rockchip: sip: Add rockchip SIP runtime service Lin Huang
2016-07-22 9:07 ` Lin Huang
2016-07-22 9:07 ` Lin Huang
2016-07-22 10:00 ` Heiko Stübner
2016-07-22 10:00 ` Heiko Stübner
2016-07-22 20:50 ` Heiko Stübner
2016-07-22 20:50 ` Heiko Stübner
2016-07-24 8:00 ` hl
2016-07-24 8:00 ` hl
2016-07-25 17:36 ` Sudeep Holla
2016-07-25 17:36 ` Sudeep Holla
2016-07-26 1:13 ` hl
2016-07-26 1:13 ` hl
2016-07-22 21:32 ` kbuild test robot
2016-07-22 21:32 ` kbuild test robot
2016-07-22 21:32 ` kbuild test robot
2016-07-26 18:29 ` Mark Rutland
2016-07-26 18:29 ` Mark Rutland
2016-07-22 9:07 ` [PATCH v3 2/7] clk: rockchip: add new clock-type for the ddrclk Lin Huang
2016-07-22 9:07 ` Lin Huang
2016-07-24 9:09 ` Heiko Stübner [this message]
2016-07-24 9:09 ` Heiko Stübner
2016-07-24 9:09 ` Heiko Stübner
2016-07-22 9:07 ` [PATCH v3 3/7] clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc Lin Huang
2016-07-22 9:07 ` Lin Huang
2016-07-22 10:08 ` Heiko Stübner
2016-07-22 10:08 ` Heiko Stübner
2016-07-22 9:07 ` [PATCH v3 4/7] clk: rockchip: rk3399: add ddrc clock support Lin Huang
2016-07-22 9:07 ` Lin Huang
2016-07-22 9:07 ` [PATCH v3 5/7] PM / devfreq: event: support rockchip dfi controller Lin Huang
2016-07-22 9:07 ` Lin Huang
2016-07-22 20:28 ` Paul Gortmaker
2016-07-22 20:28 ` Paul Gortmaker
2016-07-22 20:28 ` Paul Gortmaker
2016-07-22 9:07 ` [PATCH v3 6/7] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc Lin Huang
2016-07-22 9:07 ` Lin Huang
2016-07-22 20:24 ` Paul Gortmaker
2016-07-22 20:24 ` Paul Gortmaker
2016-07-22 20:24 ` Paul Gortmaker
2016-07-24 7:54 ` hl
2016-07-24 7:54 ` hl
2016-07-24 7:54 ` hl
2016-07-25 6:01 ` Chanwoo Choi
2016-07-25 6:01 ` Chanwoo Choi
2016-07-25 8:47 ` hl
2016-07-25 8:47 ` hl
2016-07-25 9:45 ` Chanwoo Choi
2016-07-25 9:45 ` Chanwoo Choi
2016-07-26 1:15 ` hl
2016-07-26 1:15 ` hl
2016-07-22 9:07 ` [PATCH v3 7/7] drm/rockchip: Add dmc notifier in vop driver Lin Huang
2016-07-22 9:07 ` Lin Huang
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