From: Jessica Clarke <jrtc27@jrtc27.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sagar Kadam <sagar.kadam@sifive.com>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH] dt-bindings: interrupt-controller: sifive, plic: Fix number of interrupts Date: Thu, 25 Nov 2021 16:08:03 +0000 [thread overview] Message-ID: <161F972E-7972-4001-BE19-C88F81EF8047@jrtc27.com> (raw) In-Reply-To: <20211125152233.162868-1-geert@linux-m68k.org> On 25 Nov 2021, at 15:22, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > To improve human readability and enable automatic validation, the tuples > in "interrupts-extended" properties should be grouped using angle > brackets. As the DT bindings lack an upper bound on the number of > interrupts, thus assuming one, proper grouping is currently flagged as > an error. > > Fix this by adding the missing "maxItems", limiting it to 9 interrupts > (one interrupt for a system management core, and two interrupts per core > for other cores), which should be sufficient for now. This is SiFive’s IP, so is this actually true? I would imagine it’s just parameterised and could be generated with as many targets as fit in the MMIO space, and that this is thus inaccurate. Besides, such a function change should be made separately from the grouping change. The same goes for your equivalent sifive,clint0 patch. Jess > Group the tuples in the example. > > Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> > --- > .../interrupt-controller/sifive,plic-1.0.0.yaml | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index 08d5a57ce00ff446..198b373f984f3438 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -61,6 +61,7 @@ properties: > > interrupts-extended: > minItems: 1 > + maxItems: 9 > description: > Specifies which contexts are connected to the PLIC, with "-1" specifying > that a context is not present. Each node pointed to should be a > @@ -89,12 +90,11 @@ examples: > #interrupt-cells = <1>; > compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; > interrupt-controller; > - interrupts-extended = < > - &cpu0_intc 11 > - &cpu1_intc 11 &cpu1_intc 9 > - &cpu2_intc 11 &cpu2_intc 9 > - &cpu3_intc 11 &cpu3_intc 9 > - &cpu4_intc 11 &cpu4_intc 9>; > + interrupts-extended = <&cpu0_intc 11>, > + <&cpu1_intc 11>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu2_intc 9>, > + <&cpu3_intc 11>, <&cpu3_intc 9>, > + <&cpu4_intc 11>, <&cpu4_intc 9>; > reg = <0xc000000 0x4000000>; > riscv,ndev = <10>; > }; > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
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From: Jessica Clarke <jrtc27@jrtc27.com> To: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Thomas Gleixner <tglx@linutronix.de>, Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>, Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Sagar Kadam <sagar.kadam@sifive.com>, "linux-kernel@vger.kernel.org List" <linux-kernel@vger.kernel.org>, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH] dt-bindings: interrupt-controller: sifive, plic: Fix number of interrupts Date: Thu, 25 Nov 2021 16:08:03 +0000 [thread overview] Message-ID: <161F972E-7972-4001-BE19-C88F81EF8047@jrtc27.com> (raw) In-Reply-To: <20211125152233.162868-1-geert@linux-m68k.org> On 25 Nov 2021, at 15:22, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > To improve human readability and enable automatic validation, the tuples > in "interrupts-extended" properties should be grouped using angle > brackets. As the DT bindings lack an upper bound on the number of > interrupts, thus assuming one, proper grouping is currently flagged as > an error. > > Fix this by adding the missing "maxItems", limiting it to 9 interrupts > (one interrupt for a system management core, and two interrupts per core > for other cores), which should be sufficient for now. This is SiFive’s IP, so is this actually true? I would imagine it’s just parameterised and could be generated with as many targets as fit in the MMIO space, and that this is thus inaccurate. Besides, such a function change should be made separately from the grouping change. The same goes for your equivalent sifive,clint0 patch. Jess > Group the tuples in the example. > > Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> > --- > .../interrupt-controller/sifive,plic-1.0.0.yaml | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > index 08d5a57ce00ff446..198b373f984f3438 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml > @@ -61,6 +61,7 @@ properties: > > interrupts-extended: > minItems: 1 > + maxItems: 9 > description: > Specifies which contexts are connected to the PLIC, with "-1" specifying > that a context is not present. Each node pointed to should be a > @@ -89,12 +90,11 @@ examples: > #interrupt-cells = <1>; > compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; > interrupt-controller; > - interrupts-extended = < > - &cpu0_intc 11 > - &cpu1_intc 11 &cpu1_intc 9 > - &cpu2_intc 11 &cpu2_intc 9 > - &cpu3_intc 11 &cpu3_intc 9 > - &cpu4_intc 11 &cpu4_intc 9>; > + interrupts-extended = <&cpu0_intc 11>, > + <&cpu1_intc 11>, <&cpu1_intc 9>, > + <&cpu2_intc 11>, <&cpu2_intc 9>, > + <&cpu3_intc 11>, <&cpu3_intc 9>, > + <&cpu4_intc 11>, <&cpu4_intc 9>; > reg = <0xc000000 0x4000000>; > riscv,ndev = <10>; > }; > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2021-11-25 16:08 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-25 15:22 [PATCH] dt-bindings: interrupt-controller: sifive, plic: Fix number of interrupts Geert Uytterhoeven 2021-11-25 15:22 ` [PATCH] dt-bindings: interrupt-controller: sifive,plic: " Geert Uytterhoeven 2021-11-25 16:08 ` Jessica Clarke [this message] 2021-11-25 16:08 ` [PATCH] dt-bindings: interrupt-controller: sifive, plic: " Jessica Clarke 2021-11-26 8:58 ` Geert Uytterhoeven 2021-11-26 8:58 ` Geert Uytterhoeven 2021-11-26 9:05 ` Anup Patel 2021-11-26 9:05 ` Anup Patel 2021-11-30 23:01 ` Rob Herring 2021-11-30 23:01 ` Rob Herring
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