From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: tsbogend@alpha.franken.de, paul@crapouillou.net, robh+dt@kernel.org
Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dongsheng.qiu@ingenic.com,
aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
sihui.liu@ingenic.com, jun.jiang@ingenic.com,
sernia.zhou@foxmail.com
Subject: [PATCH v2 0/3] Misc Ingenic patches.
Date: Tue, 22 Jun 2021 23:55:35 +0800 [thread overview]
Message-ID: <1624377338-75384-1-git-send-email-zhouyanjie@wanyeetech.com> (raw)
Some misc patches that don't really have any relation
between themselves.
周琰杰 (Zhou Yanjie) (3):
MIPS: X1830: Respect cell count of common properties.
MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
MIPS: CI20: Add second percpu timer for SMP.
arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++----------
arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
arch/mips/boot/dts/ingenic/x1830.dtsi | 16 +++++++++++-----
3 files changed, 29 insertions(+), 15 deletions(-)
--
2.7.4
next reply other threads:[~2021-06-22 15:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-22 15:55 周琰杰 (Zhou Yanjie) [this message]
2021-06-22 15:55 ` [PATCH v2 1/3] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
2021-06-22 15:55 ` [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-06-23 18:34 ` Paul Cercueil
2021-06-24 4:10 ` 周琰杰
2021-06-22 15:55 ` [PATCH v2 3/3] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
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