From: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
To: tsbogend@alpha.franken.de, paul@crapouillou.net, robh+dt@kernel.org
Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dongsheng.qiu@ingenic.com,
aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
sihui.liu@ingenic.com, jun.jiang@ingenic.com,
sernia.zhou@foxmail.com
Subject: [PATCH v2 3/3] MIPS: CI20: Add second percpu timer for SMP.
Date: Tue, 22 Jun 2021 23:55:38 +0800 [thread overview]
Message-ID: <1624377338-75384-4-git-send-email-zhouyanjie@wanyeetech.com> (raw)
In-Reply-To: <1624377338-75384-1-git-send-email-zhouyanjie@wanyeetech.com>
1.Add a new TCU channel as the percpu timer of core1, this is to
prepare for the subsequent SMP support. The newly added channel
will not adversely affect the current single-core state.
2.Adjust the position of TCU node to make it consistent with the
order in jz4780.dtsi file.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
New patch.
arch/mips/boot/dts/ingenic/ci20.dts | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index 8877c62..70005cc 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -118,6 +118,17 @@
assigned-clock-rates = <48000000>;
};
+&tcu {
+ /*
+ * 750 kHz for the system timers and 3 MHz for the clocksources,
+ * use channel #0 and #1 for the per cpu system timers, and use
+ * channel #2 for the clocksource.
+ */
+ assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_OST>;
+ assigned-clock-rates = <750000>, <750000>, <3000000>, <3000000>;
+};
+
&mmc0 {
status = "okay";
@@ -522,13 +533,3 @@
bias-disable;
};
};
-
-&tcu {
- /*
- * 750 kHz for the system timer and 3 MHz for the clocksource,
- * use channel #0 for the system timer, #1 for the clocksource.
- */
- assigned-clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
- <&tcu TCU_CLK_OST>;
- assigned-clock-rates = <750000>, <3000000>, <3000000>;
-};
--
2.7.4
prev parent reply other threads:[~2021-06-22 15:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-22 15:55 [PATCH v2 0/3] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
2021-06-22 15:55 ` [PATCH v2 1/3] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
2021-06-22 15:55 ` [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-06-23 18:34 ` Paul Cercueil
2021-06-24 4:10 ` 周琰杰
2021-06-22 15:55 ` 周琰杰 (Zhou Yanjie) [this message]
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