From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, thuth@redhat.com,
chenhuacai@loongson.cn, philmd@redhat.com, i.qemu@xen0n.name,
richard.henderson@linaro.org, laurent@vivier.eu,
peterx@redhat.com, f4bug@amsat.org, yangxiaojuan@loongson.cn,
alistair.francis@wdc.com, maobibo@loongson.cn,
pbonzini@redhat.com, bmeng.cn@gmail.com, alex.bennee@linaro.org,
gaosong@loongson.cn
Subject: [PATCH v8 15/29] target/loongarch: Add branch instruction translation
Date: Mon, 1 Nov 2021 17:51:37 +0800 [thread overview]
Message-ID: <1635760311-20015-16-git-send-email-gaosong@loongson.cn> (raw)
In-Reply-To: <1635760311-20015-1-git-send-email-gaosong@loongson.cn>
This includes:
- BEQ, BNE, BLT[U], BGE[U]
- BEQZ, BNEZ
- B
- BL
- JIRL
- BCEQZ, BCNEZ
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
---
target/loongarch/insn_trans/trans_branch.c | 85 ++++++++++++++++++++++++++++++
target/loongarch/insns.decode | 30 +++++++++++
target/loongarch/translate.c | 1 +
3 files changed, 116 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_branch.c
diff --git a/target/loongarch/insn_trans/trans_branch.c b/target/loongarch/insn_trans/trans_branch.c
new file mode 100644
index 0000000..77a6ae6
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_branch.c
@@ -0,0 +1,85 @@
+/*
+ * LoongArch translate functions
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+static bool trans_b(DisasContext *ctx, arg_b *a)
+{
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + (a->offs << 2));
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_bl(DisasContext *ctx, arg_bl *a)
+{
+ tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + (a->offs << 2));
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+
+ tcg_gen_addi_tl(cpu_pc, src1, (a->offs16) << 2);
+ tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
+ tcg_gen_lookup_and_goto_ptr();
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
+static void gen_bc(DisasContext *ctx, TCGv src1, TCGv src2,
+ target_long offs, TCGCond cond)
+{
+ TCGLabel *l = gen_new_label();
+ tcg_gen_brcond_tl(cond, src1, src2, l);
+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
+ gen_set_label(l);
+ gen_goto_tb(ctx, 0, ctx->base.pc_next + offs);
+ ctx->base.is_jmp = DISAS_NORETURN;
+}
+
+static bool gen_r2_bc(DisasContext *ctx, arg_fmt_rjrdoffs16 *a, TCGCond cond)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = gpr_src(ctx, a->rd, EXT_NONE);
+
+ gen_bc(ctx, src1, src2, (a->offs16 << 2), cond);
+ return true;
+}
+
+static bool gen_rz_bc(DisasContext *ctx, arg_fmt_rjoffs21 *a, TCGCond cond)
+{
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = tcg_constant_tl(0);
+
+ gen_bc(ctx, src1, src2, (a->offs21 << 2), cond);
+ return true;
+}
+
+static bool gen_cz_bc(DisasContext *ctx, arg_fmt_cjoffs21 *a, TCGCond cond)
+{
+ TCGv src1 = tcg_temp_new();
+ TCGv src2 = tcg_constant_tl(0);
+
+ tcg_gen_ld8u_tl(src1, cpu_env,
+ offsetof(CPULoongArchState, cf[a->cj & 0x7]));
+ gen_bc(ctx, src1, src2, (a->offs21 << 2), cond);
+ return true;
+}
+
+TRANS(beq, gen_r2_bc, TCG_COND_EQ)
+TRANS(bne, gen_r2_bc, TCG_COND_NE)
+TRANS(blt, gen_r2_bc, TCG_COND_LT)
+TRANS(bge, gen_r2_bc, TCG_COND_GE)
+TRANS(bltu, gen_r2_bc, TCG_COND_LTU)
+TRANS(bgeu, gen_r2_bc, TCG_COND_GEU)
+TRANS(beqz, gen_rz_bc, TCG_COND_EQ)
+TRANS(bnez, gen_rz_bc, TCG_COND_NE)
+TRANS(bceqz, gen_cz_bc, TCG_COND_EQ)
+TRANS(bcnez, gen_cz_bc, TCG_COND_NE)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index ea776c2..077063e 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -38,6 +38,9 @@
%ca 15:3
%fcsrd 0:5
%fcsrs 5:5
+%offs21 0:s5 10:16
+%offs16 10:s16
+%offs 0:s10 10:16
#
# Argument sets
@@ -74,6 +77,11 @@
&fmt_rdcj rd cj
&fmt_fdrjrk fd rj rk
&fmt_fdrjsi12 fd rj si12
+&fmt_rjoffs21 rj offs21
+&fmt_cjoffs21 cj offs21
+&fmt_rdrjoffs16 rd rj offs16
+&fmt_offs offs
+&fmt_rjrdoffs16 rj rd offs16
#
# Formats
@@ -110,6 +118,11 @@
@fmt_rdcj .... ........ ..... ..... .. ... ..... &fmt_rdcj %rd %cj
@fmt_fdrjrk .... ........ ..... ..... ..... ..... &fmt_fdrjrk %fd %rj %rk
@fmt_fdrjsi12 .... ...... ............ ..... ..... &fmt_fdrjsi12 %fd %rj %si12
+@fmt_rjoffs21 .... .. ................ ..... ..... &fmt_rjoffs21 %rj %offs21
+@fmt_cjoffs21 .... .. ................ .. ... ..... &fmt_cjoffs21 %cj %offs21
+@fmt_rdrjoffs16 .... .. ................ ..... ..... &fmt_rdrjoffs16 %rd %rj %offs16
+@fmt_offs .... .. .......................... &fmt_offs %offs
+@fmt_rjrdoffs16 .... .. ................ ..... ..... &fmt_rjrdoffs16 %rj %rd %offs16
#
# Fixed point arithmetic operation instruction
@@ -448,3 +461,20 @@ fstgt_s 0011 10000111 01100 ..... ..... ..... @fmt_fdrjrk
fstgt_d 0011 10000111 01101 ..... ..... ..... @fmt_fdrjrk
fstle_s 0011 10000111 01110 ..... ..... ..... @fmt_fdrjrk
fstle_d 0011 10000111 01111 ..... ..... ..... @fmt_fdrjrk
+
+#
+# Branch instructions
+#
+beqz 0100 00 ................ ..... ..... @fmt_rjoffs21
+bnez 0100 01 ................ ..... ..... @fmt_rjoffs21
+bceqz 0100 10 ................ 00 ... ..... @fmt_cjoffs21
+bcnez 0100 10 ................ 01 ... ..... @fmt_cjoffs21
+jirl 0100 11 ................ ..... ..... @fmt_rdrjoffs16
+b 0101 00 .......................... @fmt_offs
+bl 0101 01 .......................... @fmt_offs
+beq 0101 10 ................ ..... ..... @fmt_rjrdoffs16
+bne 0101 11 ................ ..... ..... @fmt_rjrdoffs16
+blt 0110 00 ................ ..... ..... @fmt_rjrdoffs16
+bge 0110 01 ................ ..... ..... @fmt_rjrdoffs16
+bltu 0110 10 ................ ..... ..... @fmt_rjrdoffs16
+bgeu 0110 11 ................ ..... ..... @fmt_rjrdoffs16
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 4c9255b..502fc9d 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -191,6 +191,7 @@ static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext)
#include "insn_trans/trans_fcnv.c"
#include "insn_trans/trans_fmov.c"
#include "insn_trans/trans_fmemory.c"
+#include "insn_trans/trans_branch.c"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
1.8.3.1
next prev parent reply other threads:[~2021-11-01 10:13 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-01 9:51 [PATCH v8 00/29] Add LoongArch linux-user emulation support Song Gao
2021-11-01 9:51 ` [PATCH v8 01/29] target/loongarch: Add README Song Gao
2021-11-01 9:51 ` [PATCH v8 02/29] target/loongarch: Add core definition Song Gao
2021-11-02 8:38 ` Philippe Mathieu-Daudé
2021-11-02 12:54 ` gaosong
2021-11-01 9:51 ` [PATCH v8 03/29] target/loongarch: Add main translation routines Song Gao
2021-11-01 9:51 ` [PATCH v8 04/29] target/loongarch: Add fixed point arithmetic instruction translation Song Gao
2021-11-01 9:51 ` [PATCH v8 05/29] target/loongarch: Add fixed point shift " Song Gao
2021-11-01 9:51 ` [PATCH v8 06/29] target/loongarch: Add fixed point bit " Song Gao
2021-11-01 9:51 ` [PATCH v8 07/29] target/loongarch: Add fixed point load/store " Song Gao
2021-11-01 9:51 ` [PATCH v8 08/29] target/loongarch: Add fixed point atomic " Song Gao
2021-11-01 9:51 ` [PATCH v8 09/29] target/loongarch: Add fixed point extra " Song Gao
2021-11-01 9:51 ` [PATCH v8 10/29] target/loongarch: Add floating point arithmetic " Song Gao
2021-11-01 9:51 ` [PATCH v8 11/29] target/loongarch: Add floating point comparison " Song Gao
2021-11-01 9:51 ` [PATCH v8 12/29] target/loongarch: Add floating point conversion " Song Gao
2021-11-01 9:51 ` [PATCH v8 13/29] target/loongarch: Add floating point move " Song Gao
2021-11-01 9:51 ` [PATCH v8 14/29] target/loongarch: Add floating point load/store " Song Gao
2021-11-01 9:51 ` Song Gao [this message]
2021-11-01 9:51 ` [PATCH v8 16/29] target/loongarch: Add disassembler Song Gao
2021-11-01 9:51 ` [PATCH v8 17/29] linux-user: Add LoongArch generic header files Song Gao
2021-11-01 9:51 ` [PATCH v8 18/29] linux-user: Add LoongArch specific structures Song Gao
2021-11-01 9:51 ` [PATCH v8 19/29] linux-user: Add LoongArch signal support Song Gao
2021-11-01 9:51 ` [PATCH v8 20/29] linux-user: Add LoongArch elf support Song Gao
2021-11-01 9:51 ` [PATCH v8 21/29] linux-user: Add LoongArch syscall support Song Gao
2021-11-01 9:51 ` [PATCH v8 22/29] linux-user: Add LoongArch cpu_loop support Song Gao
2021-11-01 9:51 ` [PATCH v8 23/29] linux-user: Add host dependency for LoongArch 64-bit Song Gao
2021-11-01 9:51 ` [PATCH v8 24/29] default-configs: Add loongarch linux-user support Song Gao
2021-11-01 9:51 ` [PATCH v8 25/29] target/loongarch: Add target build suport Song Gao
2021-11-01 9:51 ` [PATCH v8 26/29] target/loongarch: 'make check-tcg' support Song Gao
2021-11-02 13:56 ` Alex Bennée
2021-11-01 9:51 ` [PATCH v8 27/29] scripts: add loongarch64 binfmt config Song Gao
2021-11-01 9:51 ` [PATCH v8 28/29] accel/tcg/user-exec: Implement CPU-specific signal handler for loongarch64 hosts Song Gao
2021-11-01 10:45 ` WANG Xuerui
2021-11-01 11:21 ` gaosong
2021-11-02 3:18 ` WANG Xuerui
2021-11-01 9:51 ` [PATCH v8 29/29] linux-user: Add safe syscall handling " Song Gao
2021-11-02 8:31 ` [PATCH v8 00/29] Add LoongArch linux-user emulation support Philippe Mathieu-Daudé
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