From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
dan.j.williams@intel.com, ira.weiny@intel.com,
vishal.l.verma@intel.com, alison.schofield@intel.com,
Jonathan.Cameron@huawei.com, dave@stgolabs.net
Subject: [PATCH v11 07/22] acpi: numa: Create enum for memory_target access coordinates indexing
Date: Thu, 12 Oct 2023 11:54:12 -0700 [thread overview]
Message-ID: <169713685275.2205276.2297863607737092588.stgit@djiang5-mobl3> (raw)
In-Reply-To: <169713674328.2205276.10184241477215488339.stgit@djiang5-mobl3>
Create enums to provide named indexing for the access coordinate array.
This is in preparation for adding generic port support which will add a
third index in the array to keep the generic port attributes separate from
the memory attributes.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
---
drivers/acpi/numa/hmat.c | 35 ++++++++++++++++++++++++-----------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/acpi/numa/hmat.c b/drivers/acpi/numa/hmat.c
index f9ff992038fa..abed728bf09d 100644
--- a/drivers/acpi/numa/hmat.c
+++ b/drivers/acpi/numa/hmat.c
@@ -57,12 +57,18 @@ struct target_cache {
struct node_cache_attrs cache_attrs;
};
+enum {
+ NODE_ACCESS_CLASS_0 = 0,
+ NODE_ACCESS_CLASS_1,
+ NODE_ACCESS_CLASS_MAX,
+};
+
struct memory_target {
struct list_head node;
unsigned int memory_pxm;
unsigned int processor_pxm;
struct resource memregions;
- struct access_coordinate coord[2];
+ struct access_coordinate coord[NODE_ACCESS_CLASS_MAX];
struct list_head caches;
struct node_cache_attrs cache_attrs;
bool registered;
@@ -338,10 +344,12 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
if (mem_hier == ACPI_HMAT_MEMORY) {
target = find_mem_target(targs[targ]);
if (target && target->processor_pxm == inits[init]) {
- hmat_update_target_access(target, type, value, 0);
+ hmat_update_target_access(target, type, value,
+ NODE_ACCESS_CLASS_0);
/* If the node has a CPU, update access 1 */
if (node_state(pxm_to_node(inits[init]), N_CPU))
- hmat_update_target_access(target, type, value, 1);
+ hmat_update_target_access(target, type, value,
+ NODE_ACCESS_CLASS_1);
}
}
}
@@ -600,10 +608,12 @@ static void hmat_register_target_initiators(struct memory_target *target)
*/
if (target->processor_pxm != PXM_INVAL) {
cpu_nid = pxm_to_node(target->processor_pxm);
- register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
+ register_memory_node_under_compute_node(mem_nid, cpu_nid,
+ NODE_ACCESS_CLASS_0);
access0done = true;
if (node_state(cpu_nid, N_CPU)) {
- register_memory_node_under_compute_node(mem_nid, cpu_nid, 1);
+ register_memory_node_under_compute_node(mem_nid, cpu_nid,
+ NODE_ACCESS_CLASS_1);
return;
}
}
@@ -644,12 +654,13 @@ static void hmat_register_target_initiators(struct memory_target *target)
}
if (best)
hmat_update_target_access(target, loc->hmat_loc->data_type,
- best, 0);
+ best, NODE_ACCESS_CLASS_0);
}
for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
cpu_nid = pxm_to_node(i);
- register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
+ register_memory_node_under_compute_node(mem_nid, cpu_nid,
+ NODE_ACCESS_CLASS_0);
}
}
@@ -681,11 +692,13 @@ static void hmat_register_target_initiators(struct memory_target *target)
clear_bit(initiator->processor_pxm, p_nodes);
}
if (best)
- hmat_update_target_access(target, loc->hmat_loc->data_type, best, 1);
+ hmat_update_target_access(target, loc->hmat_loc->data_type, best,
+ NODE_ACCESS_CLASS_1);
}
for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
cpu_nid = pxm_to_node(i);
- register_memory_node_under_compute_node(mem_nid, cpu_nid, 1);
+ register_memory_node_under_compute_node(mem_nid, cpu_nid,
+ NODE_ACCESS_CLASS_1);
}
}
@@ -746,8 +759,8 @@ static void hmat_register_target(struct memory_target *target)
if (!target->registered) {
hmat_register_target_initiators(target);
hmat_register_target_cache(target);
- hmat_register_target_perf(target, 0);
- hmat_register_target_perf(target, 1);
+ hmat_register_target_perf(target, NODE_ACCESS_CLASS_0);
+ hmat_register_target_perf(target, NODE_ACCESS_CLASS_1);
target->registered = true;
}
mutex_unlock(&target_lock);
next prev parent reply other threads:[~2023-10-12 18:54 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-12 18:53 [PATCH v11 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-10-12 18:53 ` [PATCH v11 01/22] cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute Dave Jiang
2023-10-12 18:53 ` [PATCH v11 02/22] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-10-12 18:53 ` [PATCH v11 03/22] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-10-12 18:53 ` [PATCH v11 04/22] acpi: Move common tables helper functions to common lib Dave Jiang
2023-10-12 18:54 ` [PATCH v11 05/22] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-10-12 18:54 ` [PATCH v11 06/22] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-10-28 4:51 ` Dan Williams
2023-10-12 18:54 ` Dave Jiang [this message]
2023-10-12 18:54 ` [PATCH v11 08/22] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-10-12 18:54 ` [PATCH v11 09/22] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-10-12 18:54 ` [PATCH v11 10/22] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-10-12 18:54 ` [PATCH v11 11/22] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-10-12 18:54 ` [PATCH v11 12/22] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-10-28 4:08 ` Dan Williams
2023-10-12 18:54 ` [PATCH v11 13/22] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-10-12 18:54 ` [PATCH v11 14/22] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-10-12 18:55 ` [PATCH v11 15/22] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-10-16 10:56 ` Jonathan Cameron
2023-10-12 18:55 ` [PATCH v11 16/22] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 17/22] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 18/22] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 19/22] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-10-12 18:55 ` [PATCH v11 20/22] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-10-16 10:58 ` Jonathan Cameron
2023-10-27 4:48 ` Gregory Price
2023-10-27 17:17 ` Gregory Price
2023-10-28 4:23 ` Dan Williams
2023-10-12 18:55 ` [PATCH v11 21/22] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-10-16 10:59 ` Jonathan Cameron
2023-10-12 18:55 ` [PATCH v11 22/22] cxl: Check qos_class validity on memdev probe Dave Jiang
2023-10-16 11:04 ` Jonathan Cameron
2023-10-28 4:29 ` Dan Williams
2023-10-26 22:54 ` [PATCH v11 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Gregory Price
2023-10-30 16:18 ` Dave Jiang
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