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From: Jonathan Cameron <Jonathan.Cameron@Huawei.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <dan.j.williams@intel.com>,
	<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
	<alison.schofield@intel.com>, <dave@stgolabs.net>
Subject: Re: [PATCH v11 15/22] cxl: Add support for _DSM Function for retrieving QTG ID
Date: Mon, 16 Oct 2023 11:56:14 +0100	[thread overview]
Message-ID: <20231016115614.00003d60@Huawei.com> (raw)
In-Reply-To: <169713690074.2205276.14288360792472635288.stgit@djiang5-mobl3>

On Thu, 12 Oct 2023 11:55:00 -0700
Dave Jiang <dave.jiang@intel.com> wrote:

> CXL spec v3.0 9.17.3 CXL Root Device Specific Methods (_DSM)
> 
> Add support to retrieve QTG ID via ACPI _DSM call. The _DSM call requires
> an input of an ACPI package with 4 dwords (read latency, write latency,
> read bandwidth, write bandwidth). The call returns a package with 1 WORD
> that provides the max supported QTG ID and a package that may contain 0 or
> more WORDs as the recommended QTG IDs in the recommended order.
> 
> Create a cxl_root container for the root cxl_port and provide a callback
> ->get_qos_class() in order to retrieve the QoS class. For the ACPI case,  
> the _DSM helper is used to retrieve the QTG ID and returned. A
> devm_cxl_add_root() function is added for root port setup and registration
> of the cxl_root callback operation(s).
> 
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>

Hi Dave,

One totally trivial bikeshedding comment inline. Perhaps can be tweaked by
Dan if he's otherwise happy with this series.

Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

>  
> +/**
> + * cxl_acpi_evaluate_qtg_dsm - Retrieve QTG ids via ACPI _DSM
> + * @handle: ACPI handle
> + * @coord: performance access coordinates
> + * @entries: number of QTG IDs to return
> + * @qos_class: int array provided by caller to return QTG IDs
> + *
> + * Return: number of QTG IDs returned, or -errno for errors
> + *
> + * Issue QTG _DSM with accompanied bandwidth and latency data in order to get
> + * the QTG IDs that are suitable for the performance point in order of most
> + * suitable to least suitable. Write back array of QTG IDs and return the
> + * actual number of QTG IDs written back.
> + */
> +static int
> +cxl_acpi_evaluate_qtg_dsm(acpi_handle handle, struct access_coordinate *coord,
> +			  int entries, int *qos_class)
> +{
> +	union acpi_object *out_obj, *out_buf, *pkg;
> +	union acpi_object in_array[4] = {
> +		[0].integer = { ACPI_TYPE_INTEGER, coord->read_latency },
> +		[1].integer = { ACPI_TYPE_INTEGER, coord->write_latency },
> +		[2].integer = { ACPI_TYPE_INTEGER, coord->read_bandwidth },
> +		[3].integer = { ACPI_TYPE_INTEGER, coord->write_bandwidth },
> +	};
> +	union acpi_object in_obj = {
> +		.package = {
> +			.type = ACPI_TYPE_PACKAGE,
> +			.count = 4,
> +			.elements = in_array,
> +		},
> +	};
> +	int count, pkg_entries, i;
> +	u16 max_qtg;
> +	int rc;
> +
> +	if (!entries)
> +		return -EINVAL;
> +
> +	out_obj = acpi_evaluate_dsm(handle, &acpi_cxl_qtg_id_guid, 1, 1, &in_obj);
> +	if (!out_obj)
> +		return -ENXIO;
> +
> +	if (out_obj->type != ACPI_TYPE_PACKAGE) {
> +		rc = -ENXIO;
> +		goto out;
> +	}
> +
> +	/* Check Max QTG ID */
> +	pkg = &out_obj->package.elements[0];

Totally trivial, but pkg seems an odd name for something that isn't a package.

> +	if (pkg->type != ACPI_TYPE_INTEGER) {
> +		rc = -ENXIO;
> +		goto out;
> +	}
> +
> +	max_qtg = pkg->integer.value;
> +
> +	/* It's legal to have 0 QTG entries */
> +	pkg_entries = out_obj->package.count;
> +	if (pkg_entries <= 1) {
> +		rc = 0;
> +		goto out;
> +	}
> +
> +	/* Retrieve QTG IDs package */
> +	pkg = &out_obj->package.elements[1];
> +	if (pkg->type != ACPI_TYPE_PACKAGE) {
> +		rc = -ENXIO;
> +		goto out;
> +	}
> +
> +	pkg_entries = pkg->package.count;
> +	count = min(entries, pkg_entries);
> +	for (i = 0; i < count; i++) {
> +		u16 qtg_id;
> +
> +		out_buf = &pkg->package.elements[i];
> +		if (out_buf->type != ACPI_TYPE_INTEGER) {
> +			rc = -ENXIO;
> +			goto out;
> +		}
> +
> +		qtg_id = out_buf->integer.value;
> +		if (qtg_id > max_qtg)
> +			pr_warn("QTG ID %u greater than MAX %u\n",
> +				qtg_id, max_qtg);
> +
> +		qos_class[i] = qtg_id;
> +	}
> +	rc = count;
> +
> +out:
> +	ACPI_FREE(out_obj);
> +	return rc;
> +}
> +




  reply	other threads:[~2023-10-16 10:56 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-12 18:53 [PATCH v11 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-10-12 18:53 ` [PATCH v11 01/22] cxl: Export QTG ids from CFMWS to sysfs as qos_class attribute Dave Jiang
2023-10-12 18:53 ` [PATCH v11 02/22] cxl: Add checksum verification to CDAT from CXL Dave Jiang
2023-10-12 18:53 ` [PATCH v11 03/22] cxl: Add support for reading CXL switch CDAT table Dave Jiang
2023-10-12 18:53 ` [PATCH v11 04/22] acpi: Move common tables helper functions to common lib Dave Jiang
2023-10-12 18:54 ` [PATCH v11 05/22] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-10-12 18:54 ` [PATCH v11 06/22] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-10-28  4:51   ` Dan Williams
2023-10-12 18:54 ` [PATCH v11 07/22] acpi: numa: Create enum for memory_target access coordinates indexing Dave Jiang
2023-10-12 18:54 ` [PATCH v11 08/22] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-10-12 18:54 ` [PATCH v11 09/22] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-10-12 18:54 ` [PATCH v11 10/22] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-10-12 18:54 ` [PATCH v11 11/22] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-10-12 18:54 ` [PATCH v11 12/22] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-10-28  4:08   ` Dan Williams
2023-10-12 18:54 ` [PATCH v11 13/22] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-10-12 18:54 ` [PATCH v11 14/22] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-10-12 18:55 ` [PATCH v11 15/22] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-10-16 10:56   ` Jonathan Cameron [this message]
2023-10-12 18:55 ` [PATCH v11 16/22] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 17/22] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 18/22] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-10-12 18:55 ` [PATCH v11 19/22] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-10-12 18:55 ` [PATCH v11 20/22] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-10-16 10:58   ` Jonathan Cameron
2023-10-27  4:48   ` Gregory Price
2023-10-27 17:17   ` Gregory Price
2023-10-28  4:23     ` Dan Williams
2023-10-12 18:55 ` [PATCH v11 21/22] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-10-16 10:59   ` Jonathan Cameron
2023-10-12 18:55 ` [PATCH v11 22/22] cxl: Check qos_class validity on memdev probe Dave Jiang
2023-10-16 11:04   ` Jonathan Cameron
2023-10-28  4:29     ` Dan Williams
2023-10-26 22:54 ` [PATCH v11 00/22] cxl: Add support for QTG ID retrieval for CXL subsystem Gregory Price
2023-10-30 16:18   ` Dave Jiang

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