Re: [PATCH 5/7] target/arm: Implement HCR_EL2.TICAB,TOCU traps

From: Richard Henderson <richard.henderson@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>,
	qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH 5/7] target/arm: Implement HCR_EL2.TICAB,TOCU traps
Date: Sat, 29 Oct 2022 06:43:57 +1100	[thread overview]
Message-ID: <17d1bc6a-a30e-ee8c-b3c3-a74dce657375@linaro.org> (raw)
In-Reply-To: <20221028134002.730598-6-peter.maydell@linaro.org>

On 10/29/22 00:40, Peter Maydell wrote:
> For FEAT_EVT, the HCR_EL2.TICAB bit allows trapping of the ICIALLUIS
> and IC IALLUIS cache maintenance instructions.
> 
> The HCR_EL2.TOCU bit traps all the other cache maintenance
> instructions that operate to the point of unification:
>   AArch64 IC IVAU, IC IALLU, DC CVAU
>   AArch32 ICIMVAU, ICIALLU, DCCMVAU
> 
> The two trap bits between them cover all of the cache maintenance
> instructions which must also check the HCR_TPU flag.  Turn the old
> aa64_cacheop_pou_access() function into a helper function which takes
> the set of HCR_EL2 flags to check as an argument, and call it from
> new access_ticab() and access_tocu() functions as appropriate for
> each cache op.
> 
> Signed-off-by: Peter Maydell<peter.maydell@linaro.org>
> ---
>   target/arm/helper.c | 36 +++++++++++++++++++++++-------------
>   1 file changed, 23 insertions(+), 13 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~