From: "Michał Mirosław" <mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> To: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org Subject: [PATCH 4/9] ARM: trusted_foundations: enable L2x0 cache via firmware_ops Date: Thu, 20 Jul 2017 02:29:24 +0200 [thread overview] Message-ID: <1d12ea86cca40749731a594afc165830c0b2463d.1500510157.git.mirq-linux@rere.qmqm.pl> (raw) In-Reply-To: <cover.1500510157.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> Use firmware_ops to provide hook for cache initialization through Trusted Foundations firmware, as some writes need Secure mode. Signed-off-by: Michał Mirosław <mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> --- arch/arm/firmware/trusted_foundations.c | 46 ++++++++++++++++++++++++++++++ arch/arm/include/asm/hardware/cache-l2x0.h | 1 + arch/arm/mm/cache-l2x0.c | 10 ++++++- 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 3fb1b5a1dce9..81ff71b87438 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -17,11 +17,19 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/of.h> +#include <asm/io.h> #include <asm/firmware.h> +#include <asm/outercache.h> +#include <asm/hardware/cache-l2x0.h> #include <asm/trusted_foundations.h> +#define TF_CACHE_MAINT 0xfffff100 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 +#define TF_CACHE_INIT 1 +#define TF_CACHE_FLUSH 2 +#define TF_CACHE_REENABLE 4 + #define TF_CPU_PM 0xfffffffc #define TF_CPU_PM_S3 0xffffffe3 #define TF_CPU_PM_S2 0xffffffe6 @@ -63,9 +71,47 @@ static int tf_prepare_idle(void) return 0; } +#ifdef CONFIG_CACHE_L2X0 +static void tf_write_sec(unsigned long val, unsigned reg) +{ + unsigned long cur = readl_relaxed(l2x0_base + reg); + + pr_warn("TF: ignoring write_sec[0x%x]: 0x%08lx -> 0x%08lx\n", reg, cur, val); +} + +static void tf_disable_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_FLUSH, l2x0_way_mask); +} + +static void tf_resume_cache(void) +{ + unsigned long aux_val = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_REENABLE, aux_val); +} + +static void tf_configure_cache(const struct l2x0_regs *regs) +{ + outer_cache.disable = tf_disable_cache; + outer_cache.resume = tf_resume_cache; +} + +static int tf_init_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_INIT, 0); + + outer_cache.write_sec = tf_write_sec; + outer_cache.configure = tf_configure_cache; + return 0; +} +#endif /* CONFIG_CACHE_L2X0 */ + static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, .prepare_idle = tf_prepare_idle, +#ifdef CONFIG_CACHE_L2X0 + .l2x0_init = tf_init_cache, +#endif }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 492de655e4f3..665eb0758417 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -194,6 +194,7 @@ struct l2x0_regs { }; extern void __iomem *l2x0_base; +extern u32 l2x0_way_mask; /* Bitmask of active ways */ extern struct l2x0_regs l2x0_saved_regs; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index bbfbc18399f9..f1268e9b35f0 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -30,6 +30,7 @@ #include <asm/cp15.h> #include <asm/cputype.h> #include <asm/hardware/cache-l2x0.h> +#include <asm/firmware.h> #include "cache-tauros3.h" #include "cache-aurora-l2.h" @@ -37,6 +38,7 @@ struct l2c_init_data { const char *type; unsigned way_size_0; unsigned num_lock; + void (*init)(void __iomem *, u32 *, u32 *); void (*of_parse)(const struct device_node *, u32 *, u32 *); void (*enable)(void __iomem *, unsigned); void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); @@ -50,11 +52,11 @@ struct l2c_init_data { static const struct l2c_init_data *l2x0_data; static DEFINE_RAW_SPINLOCK(l2x0_lock); -static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; void __iomem *l2x0_base; +u32 l2x0_way_mask; /* Bitmask of active ways */ struct l2x0_regs l2x0_saved_regs; static bool l2x0_bresp_disable; @@ -1760,6 +1762,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) u32 cache_id; u32 cache_level = 2; bool nosync = false; + int err; np = of_find_matching_node(NULL, l2x0_ids); if (!np) @@ -1792,6 +1795,11 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) nosync = of_property_read_bool(np, "arm,outer-sync-disable"); + /* Call firmware init */ + err = call_firmware_op(l2x0_init); + if (err && err != -ENOSYS) + return err; + /* Read back current (default) hardware configuration */ if (data->save) data->save(l2x0_base); -- 2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: mirq-linux@rere.qmqm.pl (Michał Mirosław) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH 4/9] ARM: trusted_foundations: enable L2x0 cache via firmware_ops Date: Thu, 20 Jul 2017 02:29:24 +0200 [thread overview] Message-ID: <1d12ea86cca40749731a594afc165830c0b2463d.1500510157.git.mirq-linux@rere.qmqm.pl> (raw) In-Reply-To: <cover.1500510157.git.mirq-linux@rere.qmqm.pl> Use firmware_ops to provide hook for cache initialization through Trusted Foundations firmware, as some writes need Secure mode. Signed-off-by: Micha? Miros?aw <mirq-linux@rere.qmqm.pl> --- arch/arm/firmware/trusted_foundations.c | 46 ++++++++++++++++++++++++++++++ arch/arm/include/asm/hardware/cache-l2x0.h | 1 + arch/arm/mm/cache-l2x0.c | 10 ++++++- 3 files changed, 56 insertions(+), 1 deletion(-) diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c index 3fb1b5a1dce9..81ff71b87438 100644 --- a/arch/arm/firmware/trusted_foundations.c +++ b/arch/arm/firmware/trusted_foundations.c @@ -17,11 +17,19 @@ #include <linux/kernel.h> #include <linux/init.h> #include <linux/of.h> +#include <asm/io.h> #include <asm/firmware.h> +#include <asm/outercache.h> +#include <asm/hardware/cache-l2x0.h> #include <asm/trusted_foundations.h> +#define TF_CACHE_MAINT 0xfffff100 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 +#define TF_CACHE_INIT 1 +#define TF_CACHE_FLUSH 2 +#define TF_CACHE_REENABLE 4 + #define TF_CPU_PM 0xfffffffc #define TF_CPU_PM_S3 0xffffffe3 #define TF_CPU_PM_S2 0xffffffe6 @@ -63,9 +71,47 @@ static int tf_prepare_idle(void) return 0; } +#ifdef CONFIG_CACHE_L2X0 +static void tf_write_sec(unsigned long val, unsigned reg) +{ + unsigned long cur = readl_relaxed(l2x0_base + reg); + + pr_warn("TF: ignoring write_sec[0x%x]: 0x%08lx -> 0x%08lx\n", reg, cur, val); +} + +static void tf_disable_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_FLUSH, l2x0_way_mask); +} + +static void tf_resume_cache(void) +{ + unsigned long aux_val = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_REENABLE, aux_val); +} + +static void tf_configure_cache(const struct l2x0_regs *regs) +{ + outer_cache.disable = tf_disable_cache; + outer_cache.resume = tf_resume_cache; +} + +static int tf_init_cache(void) +{ + tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_INIT, 0); + + outer_cache.write_sec = tf_write_sec; + outer_cache.configure = tf_configure_cache; + return 0; +} +#endif /* CONFIG_CACHE_L2X0 */ + static const struct firmware_ops trusted_foundations_ops = { .set_cpu_boot_addr = tf_set_cpu_boot_addr, .prepare_idle = tf_prepare_idle, +#ifdef CONFIG_CACHE_L2X0 + .l2x0_init = tf_init_cache, +#endif }; void register_trusted_foundations(struct trusted_foundations_platform_data *pd) diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 492de655e4f3..665eb0758417 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -194,6 +194,7 @@ struct l2x0_regs { }; extern void __iomem *l2x0_base; +extern u32 l2x0_way_mask; /* Bitmask of active ways */ extern struct l2x0_regs l2x0_saved_regs; #endif /* __ASSEMBLY__ */ diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index bbfbc18399f9..f1268e9b35f0 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -30,6 +30,7 @@ #include <asm/cp15.h> #include <asm/cputype.h> #include <asm/hardware/cache-l2x0.h> +#include <asm/firmware.h> #include "cache-tauros3.h" #include "cache-aurora-l2.h" @@ -37,6 +38,7 @@ struct l2c_init_data { const char *type; unsigned way_size_0; unsigned num_lock; + void (*init)(void __iomem *, u32 *, u32 *); void (*of_parse)(const struct device_node *, u32 *, u32 *); void (*enable)(void __iomem *, unsigned); void (*fixup)(void __iomem *, u32, struct outer_cache_fns *); @@ -50,11 +52,11 @@ struct l2c_init_data { static const struct l2c_init_data *l2x0_data; static DEFINE_RAW_SPINLOCK(l2x0_lock); -static u32 l2x0_way_mask; /* Bitmask of active ways */ static u32 l2x0_size; static unsigned long sync_reg_offset = L2X0_CACHE_SYNC; void __iomem *l2x0_base; +u32 l2x0_way_mask; /* Bitmask of active ways */ struct l2x0_regs l2x0_saved_regs; static bool l2x0_bresp_disable; @@ -1760,6 +1762,7 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) u32 cache_id; u32 cache_level = 2; bool nosync = false; + int err; np = of_find_matching_node(NULL, l2x0_ids); if (!np) @@ -1792,6 +1795,11 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask) nosync = of_property_read_bool(np, "arm,outer-sync-disable"); + /* Call firmware init */ + err = call_firmware_op(l2x0_init); + if (err && err != -ENOSYS) + return err; + /* Read back current (default) hardware configuration */ if (data->save) data->save(l2x0_base); -- 2.11.0
next prev parent reply other threads:[~2017-07-20 0:29 UTC|newest] Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-07-20 0:29 [PATCH 0/9] Bringing Asus TF300T support to mainline Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław [not found] ` <cover.1500510157.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> 2017-07-20 0:29 ` [PATCH 2/9] arm: cache-l2x0: remove duplicate warning Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław 2017-07-20 0:29 ` [PATCH 3/9] arm: cache-l2x0: share l2x0_base Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław [not found] ` <eb104cfdf44ef9bf7b4f271555e1496d2bf781bf.1500510157.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> 2017-10-05 16:48 ` Mark Rutland 2017-10-05 16:48 ` Mark Rutland 2017-12-19 23:10 ` Russell King - ARM Linux 2017-12-19 23:10 ` Russell King - ARM Linux 2017-07-20 0:29 ` [PATCH 1/9] ARM: enable secure platform-only erratas Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław [not found] ` <77ce738c15b992a92bee3a18e5468342fb2dc5ab.1500510157.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> 2017-10-05 15:53 ` Dmitry Osipenko 2017-10-05 15:53 ` Dmitry Osipenko 2017-10-05 18:16 ` Dmitry Osipenko 2017-10-05 18:16 ` Dmitry Osipenko [not found] ` <bdff72b9-8ebd-a426-b27b-fe055d45cfb1-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2017-12-19 23:28 ` Russell King - ARM Linux 2017-12-19 23:28 ` Russell King - ARM Linux [not found] ` <20171219232810.GI10595-l+eeeJia6m9URfEZ8mYm6t73F7V6hmMc@public.gmane.org> 2017-12-20 12:49 ` Dmitry Osipenko 2017-12-20 12:49 ` Dmitry Osipenko 2017-07-20 0:29 ` [PATCH 5/9] ARM: trusted_foundations: announce firmware version Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław [this message] 2017-07-20 0:29 ` [PATCH 4/9] ARM: trusted_foundations: enable L2x0 cache via firmware_ops Michał Mirosław [not found] ` <1d12ea86cca40749731a594afc165830c0b2463d.1500510157.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> 2017-10-05 16:24 ` Dmitry Osipenko 2017-10-05 16:24 ` Dmitry Osipenko 2017-12-19 18:56 ` Dmitry Osipenko 2017-12-19 18:56 ` Dmitry Osipenko 2017-07-20 0:29 ` [PATCH 8/9] ARM: tegra: avoid touching Secure registers in reset handler Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław 2017-07-20 0:29 ` [PATCH 6/9] ARM: init: update secondary_data register documentation Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław [not found] ` <a6e5e735ebae32a433e501188a86082efc8b0b52.1500510157.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> 2017-12-19 23:16 ` Russell King - ARM Linux 2017-12-19 23:16 ` Russell King - ARM Linux 2017-07-20 0:29 ` [PATCH 7/9] ARM: tegra: enable cache via TF Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław [not found] ` <6a164b2270a3e996c083e94bf5b1e27028c1135e.1500510157.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> 2017-12-19 19:07 ` Dmitry Osipenko 2017-12-19 19:07 ` Dmitry Osipenko 2017-12-19 23:21 ` Russell King - ARM Linux 2017-12-19 23:21 ` Russell King - ARM Linux 2017-07-20 0:29 ` [PATCH 9/9] ARM: tegra: fix sleeping while atomic in CPU idle Michał Mirosław 2017-07-20 0:29 ` Michał Mirosław [not found] ` <0a0600cdbcc9a71134105043c3e2ace84bab7c5a.1500510157.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> 2017-07-20 12:45 ` Jon Hunter 2017-07-20 12:45 ` Jon Hunter [not found] ` <378bf911-147e-f800-2de4-591e160528f0-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2017-07-20 16:28 ` Michał Mirosław 2017-07-20 16:28 ` Michał Mirosław [not found] ` <20170720162852.rh565t5as2tbe6np-cHozx32mtrEEUmgCuDUIdw@public.gmane.org> 2017-07-21 8:15 ` Jon Hunter 2017-07-21 8:15 ` Jon Hunter 2017-07-20 7:48 ` [PATCH 0/9] Bringing Asus TF300T support to mainline Mikko Perttunen 2017-07-20 7:48 ` Mikko Perttunen [not found] ` <a4149270-561a-4190-4c4e-c164bd91446e-/1wQRMveznE@public.gmane.org> 2017-07-20 15:07 ` Michał Mirosław 2017-07-20 15:07 ` Michał Mirosław 2017-10-04 21:25 ` Michał Mirosław 2017-10-04 21:25 ` Michał Mirosław [not found] ` <20171004212534.uosfz6757bbds2c5-cHozx32mtrEEUmgCuDUIdw@public.gmane.org> 2017-10-05 15:52 ` Dmitry Osipenko 2017-10-05 15:52 ` Dmitry Osipenko [not found] ` <dcbbc541-60c1-8af5-25ea-927629447a55-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2017-10-05 16:07 ` Dmitry Osipenko 2017-10-05 16:07 ` Dmitry Osipenko -- strict thread matches above, loose matches on Subject: below -- 2017-07-20 0:14 Michał Mirosław [not found] ` <cover.1500509346.git.mirq-linux-CoA6ZxLDdyEEUmgCuDUIdw@public.gmane.org> 2017-07-20 0:14 ` [PATCH 4/9] ARM: trusted_foundations: enable L2x0 cache via firmware_ops Michał Mirosław
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