From: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>,
linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org,
khilman@baylibre.com, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org
Subject: Re: [PATCH 2/6] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
Date: Wed, 02 Oct 2019 11:04:42 +0200 [thread overview]
Message-ID: <1jbluzr00l.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <CAFBinCCED4YWYkdtrfrC80C8WLE=fyMJdjTa3wFNMJgC1OsoOA@mail.gmail.com>
On Tue 01 Oct 2019 at 20:53, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>
> [...]
>> > +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
>> > + .hws = {
>> > + [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
>> > + [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
>>
>> I wonder if onecell is not overkill for this driver. We won't expose the
>> DCO, so only the post divider remains
>>
>> Do you expect this provider to have more than one leaf clock ?
>> If not, maybe you could use of_clk_hw_simple_get() instead ?
> there's some more clock bits in DDR_CLK_CNTL - the public A311D
> datasheet has a description for these bits but I'm not sure they do
> the same on Meson8/Meson8b/Meson8m2
> all I know is that some magic bytes are written to DDR_CLK_CNTL in the
> old u-boot code
>
> that's why I don't want to make any assumptions and play safe here (by
> using a onecell clock provider)
Understood. Let's keep onecell then.
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: devicetree@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>,
khilman@baylibre.com, linux-kernel@vger.kernel.org,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/6] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
Date: Wed, 02 Oct 2019 11:04:42 +0200 [thread overview]
Message-ID: <1jbluzr00l.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <CAFBinCCED4YWYkdtrfrC80C8WLE=fyMJdjTa3wFNMJgC1OsoOA@mail.gmail.com>
On Tue 01 Oct 2019 at 20:53, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>
> [...]
>> > +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
>> > + .hws = {
>> > + [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
>> > + [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
>>
>> I wonder if onecell is not overkill for this driver. We won't expose the
>> DCO, so only the post divider remains
>>
>> Do you expect this provider to have more than one leaf clock ?
>> If not, maybe you could use of_clk_hw_simple_get() instead ?
> there's some more clock bits in DDR_CLK_CNTL - the public A311D
> datasheet has a description for these bits but I'm not sure they do
> the same on Meson8/Meson8b/Meson8m2
> all I know is that some magic bytes are written to DDR_CLK_CNTL in the
> old u-boot code
>
> that's why I don't want to make any assumptions and play safe here (by
> using a onecell clock provider)
Understood. Let's keep onecell then.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Jerome Brunet <jbrunet@baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: devicetree@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>,
khilman@baylibre.com, linux-kernel@vger.kernel.org,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/6] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller
Date: Wed, 02 Oct 2019 11:04:42 +0200 [thread overview]
Message-ID: <1jbluzr00l.fsf@starbuckisacylon.baylibre.com> (raw)
In-Reply-To: <CAFBinCCED4YWYkdtrfrC80C8WLE=fyMJdjTa3wFNMJgC1OsoOA@mail.gmail.com>
On Tue 01 Oct 2019 at 20:53, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>
> [...]
>> > +static struct clk_hw_onecell_data meson8_ddr_clk_hw_onecell_data = {
>> > + .hws = {
>> > + [DDR_CLKID_DDR_PLL_DCO] = &meson8_ddr_pll_dco.hw,
>> > + [DDR_CLKID_DDR_PLL] = &meson8_ddr_pll.hw,
>>
>> I wonder if onecell is not overkill for this driver. We won't expose the
>> DCO, so only the post divider remains
>>
>> Do you expect this provider to have more than one leaf clock ?
>> If not, maybe you could use of_clk_hw_simple_get() instead ?
> there's some more clock bits in DDR_CLK_CNTL - the public A311D
> datasheet has a description for these bits but I'm not sure they do
> the same on Meson8/Meson8b/Meson8m2
> all I know is that some magic bytes are written to DDR_CLK_CNTL in the
> old u-boot code
>
> that's why I don't want to make any assumptions and play safe here (by
> using a onecell clock provider)
Understood. Let's keep onecell then.
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
next prev parent reply other threads:[~2019-10-02 9:04 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-21 15:18 [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 1/6] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-10-02 14:19 ` Rob Herring
2019-10-02 14:19 ` Rob Herring
2019-10-02 14:19 ` Rob Herring
2019-09-21 15:18 ` [PATCH 2/6] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-10-01 13:29 ` Jerome Brunet
2019-10-01 13:29 ` Jerome Brunet
2019-10-01 13:29 ` Jerome Brunet
2019-10-01 18:53 ` Martin Blumenstingl
2019-10-01 18:53 ` Martin Blumenstingl
2019-10-01 18:53 ` Martin Blumenstingl
2019-10-01 18:53 ` Martin Blumenstingl
2019-10-02 9:04 ` Jerome Brunet [this message]
2019-10-02 9:04 ` Jerome Brunet
2019-10-02 9:04 ` Jerome Brunet
2019-09-21 15:18 ` [PATCH 3/6] clk: meson: meson8b: use of_clk_hw_register to register the clocks Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 4/6] clk: meson: meson8b: add the ddr_pll input for the audio clocks Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 5/6] ARM: dts: meson8: add the DDR clock controller Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 6/6] ARM: dts: meson8b: " Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-21 15:18 ` Martin Blumenstingl
2019-09-23 10:06 ` [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b Jerome Brunet
2019-09-23 10:06 ` Jerome Brunet
2019-09-23 10:06 ` Jerome Brunet
2019-09-23 10:06 ` Jerome Brunet
2019-09-23 20:49 ` Martin Blumenstingl
2019-09-23 20:49 ` Martin Blumenstingl
2019-09-23 20:49 ` Martin Blumenstingl
2019-10-01 13:33 ` Jerome Brunet
2019-10-01 13:33 ` Jerome Brunet
2019-10-01 13:33 ` Jerome Brunet
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