From: Russell King - ARM Linux <linux@arm.linux.org.uk>
To: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/3] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONACHED L1 entries
Date: Sun, 8 Aug 2010 12:34:04 +0100 [thread overview]
Message-ID: <20100808113403.GA23623@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <1281262672-27626-1-git-send-email-santosh.shilimkar@ti.com>
On Sun, Aug 08, 2010 at 03:47:52PM +0530, Santosh Shilimkar wrote:
> @@ -475,6 +486,9 @@ static void __init build_mem_type_table(void)
> mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
> mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
> mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
> + mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
> + mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask | cp->pmd;
> + mem_types[MT_MEMORY_NONCACHED].prot_pte |= kern_pgprot;
This is wrong - it will result in the non-cached memory mapped in as
sections having the same cache settings as MT_MEMORY - in other
words, probably write back.
WARNING: multiple messages have this Message-ID (diff)
From: linux@arm.linux.org.uk (Russell King - ARM Linux)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/3] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONACHED L1 entries
Date: Sun, 8 Aug 2010 12:34:04 +0100 [thread overview]
Message-ID: <20100808113403.GA23623@n2100.arm.linux.org.uk> (raw)
In-Reply-To: <1281262672-27626-1-git-send-email-santosh.shilimkar@ti.com>
On Sun, Aug 08, 2010 at 03:47:52PM +0530, Santosh Shilimkar wrote:
> @@ -475,6 +486,9 @@ static void __init build_mem_type_table(void)
> mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
> mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
> mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
> + mem_types[MT_MEMORY].prot_pte |= kern_pgprot;
> + mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask | cp->pmd;
> + mem_types[MT_MEMORY_NONCACHED].prot_pte |= kern_pgprot;
This is wrong - it will result in the non-cached memory mapped in as
sections having the same cache settings as MT_MEMORY - in other
words, probably write back.
next prev parent reply other threads:[~2010-08-08 11:34 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-08-08 10:17 [PATCH 1/3] ARM: mmu: Setup MT_MEMORY and MT_MEMORY_NONACHED L1 entries Santosh Shilimkar
2010-08-08 10:17 ` Santosh Shilimkar
2010-08-08 11:34 ` Russell King - ARM Linux [this message]
2010-08-08 11:34 ` Russell King - ARM Linux
2010-08-08 11:46 ` Shilimkar, Santosh
2010-08-08 11:46 ` Shilimkar, Santosh
2010-08-09 9:19 ` Shilimkar, Santosh
2018-06-19 20:26 ` Shilimkar, Santosh
2010-08-08 11:35 ` Russell King - ARM Linux
2010-08-08 11:35 ` Russell King - ARM Linux
2010-08-08 11:44 ` Shilimkar, Santosh
2010-08-08 11:44 ` Shilimkar, Santosh
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