[Bug 38800] glXSwapBuffersMscOML is slow on AMD Fusion but not on Intel 945 w/Atom - bugzilla-daemon

From: bugzilla-daemon@freedesktop.org
To: dri-devel@lists.freedesktop.org
Subject: [Bug 38800] glXSwapBuffersMscOML is slow on AMD Fusion but not on Intel 945 w/Atom
Date: Fri,  8 Jul 2011 04:32:58 -0700 (PDT)	[thread overview]
Message-ID: <20110708113258.41D6113004F@annarchy.freedesktop.org> (raw)
In-Reply-To: <bug-38800-502@http.bugs.freedesktop.org/>

https://bugs.freedesktop.org/show_bug.cgi?id=38800

--- Comment #41 from Simon Farnsworth <simon.farnsworth@onelan.co.uk> 2011-07-08 04:32:57 PDT ---
Created an attachment (id=48888)
 View: https://bugs.freedesktop.org/attachment.cgi?id=48888
 Review: https://bugs.freedesktop.org/review?bug=38800&attachment=48888

dmesg snippet showing which bit of the IRQ handler is slow

I've come up to airlied drm-fixes d61a06862ba8c14466e1dd718cac460da0465ddd and
applied the attached patch to help track my IRQ latencies down.

[   83.799765] [drm:evergreen_irq_process], r600_irq_process start: rptr 15728,
wptr 15744
[   83.799785] [drm:evergreen_irq_process], About to evergreen_irq_ack
[   83.799794] [drm:evergreen_irq_ack], Before register reads
[   83.799804] [drm:evergreen_irq_ack], Read DISP_INTERRUPT_STATUS
[   83.799813] [drm:evergreen_irq_ack], Read DISP_INTERRUPT_STATUS_CONTINUE
[   83.799823] [drm:evergreen_irq_ack], Read DISP_INTERRUPT_STATUS_CONTINUE2
[   83.799833] [drm:evergreen_irq_ack], Read DISP_INTERRUPT_STATUS_CONTINUE3
[   83.799842] [drm:evergreen_irq_ack], Read DISP_INTERRUPT_STATUS_CONTINUE4
[   83.799852] [drm:evergreen_irq_ack], Read DISP_INTERRUPT_STATUS_CONTINUE5
[   83.799861] [drm:evergreen_irq_ack], Read GRPH_INT_STATUS +
EVERGREEN_CRTC0_REGISTER_OFFSET
[   83.799868] [drm:evergreen_irq_ack], Read GRPH_INT_STATUS +
EVERGREEN_CRTC1_REGISTER_OFFSET
[   83.799955] [drm:evergreen_irq_ack], Read GRPH_INT_STATUS +
EVERGREEN_CRTC2_REGISTER_OFFSET
[   83.800042] [drm:evergreen_irq_ack], Read GRPH_INT_STATUS +
EVERGREEN_CRTC3_REGISTER_OFFSET
[   83.800130] [drm:evergreen_irq_ack], Read GRPH_INT_STATUS +
EVERGREEN_CRTC4_REGISTER_OFFSET
[   83.800217] [drm:evergreen_irq_ack], Read GRPH_INT_STATUS +
EVERGREEN_CRTC5_REGISTER_OFFSET
[   83.800222] [drm:evergreen_irq_ack], After register reads
[   83.800226] [drm:evergreen_irq_ack], Before pageflip occurred
[   83.800230] [drm:evergreen_irq_ack], After pageflip occurred
[   83.800234] [drm:evergreen_irq_ack], Before vblank/vline
[   83.800238] [drm:evergreen_irq_ack], After vblank/vline
[   83.800242] [drm:evergreen_irq_ack], Before HPD
[   83.800246] [drm:evergreen_irq_ack], After HPD
[   83.800250] [drm:evergreen_irq_process], Done evergreen_irq_ack
[   83.800261] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 1 : v 5
p(736,12)@ 1310124309.668537 -> 1310124309.668370 [e 2 us, 0 rep]

is the resulting block in dmesg when I'm trying to pageflip. You can see that
the slow bit is reading GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET to
GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, at about 80usec each; if I
understand the differences between discrete Evergreen and Fusion properly, it's
being very slow to read interrupt statuses for CRTCs that don't exist in
silicon.

What's the best way to handle this? A "sumo" specific irq_process function and
helpers in evergreen.c, and appropriate changes to radeon_asic.c?

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