From: Catalin Marinas <catalin.marinas@arm.com> To: Olof Johansson <olof@lixom.net> Cc: "linux-arch@vger.kernel.org" <linux-arch@vger.kernel.org>, "linux-arm-kernel@lists.infradead.org" <linux-arm-kernel@lists.infradead.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Arnd Bergmann <arnd@arndb.de>, Will Deacon <Will.Deacon@arm.com> Subject: Re: [PATCH v2 02/31] arm64: Kernel booting and initialisation Date: Wed, 15 Aug 2012 18:37:11 +0100 [thread overview] Message-ID: <20120815173711.GC14264@arm.com> (raw) In-Reply-To: <20120814230645.GA19607@quad.lixom.net> Hi Olof, On Wed, Aug 15, 2012 at 12:06:45AM +0100, Olof Johansson wrote: > On Tue, Aug 14, 2012 at 06:52:03PM +0100, Catalin Marinas wrote: > > +Before jumping into the kernel, the following conditions must be met: > > + > > +- Quiesce all DMA capable devices so that memory does not get > > + corrupted by bogus network packets or disk data. This will save > > + you many hours of debug. > > + > > +- Primary CPU general-purpose register settings > > + x0 = physical address of device tree blob (dtb) in system RAM. > > + > > +- CPU mode > > + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, > > + IRQ and FIQ). > > + The CPU must be in either EL2 (RECOMMENDED in order to have access to > > + the virtualisation extensions) or non-secure EL1. > > + > > +- Caches, MMUs > > + The MMU must be off. > > + Instruction cache may be on or off. > > + Data cache must be off and invalidated. > > + > > +- Architected timers > > + CNTFRQ must be programmed with the timer frequency. > > + If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) > > + set where available. > > + > > +- Coherency > > + All CPUs to be booted by the kernel must be part of the same coherency > > + domain on entry to the kernel. This may require IMPLEMENTATION DEFINED > > + initialisation to enable the receiving of maintenance operations on > > + each CPU. > > + > > +- System registers > > + All writable architected system registers at the exception level where > > + the kernel image will be entered must be initialised by software at a > > + higher exception level to prevent execution in an UNKNOWN state. > > Given the recent development of ARM platforms, you might want to mandate > the state of IOMMUs as well (they should probably be off, since there > should be no active DMA activity). Graphics would be the exception to > this, since if you want to keep scanning out a splash screen, you'll > have to keep doing DMA... We'll enhance this document as we get hardware as it's not clear whether we can simply mandate it to be off. We may have situations with some simple IOMMU that is previously set up by the firmware and the kernel doesn't get access to it. One example is the System MMU from ARM that supports stage 2 (hypervisor) translations and you just run a guest kernel without any control of the IOMMU. > > +- The primary CPU must jump directly to the first instruction of the > > + kernel image. The device tree blob passed by this CPU must contain > > + for each CPU node: > > + > > + 1. An 'enable-method' property. Currently, the only supported value > > + for this field is the string "spin-table". > > + > > + 2. A 'cpu-release-addr' property identifying a 64-bit, > > + zero-initialised memory location. > > These would be good to have documented in the > Documentation/devicetree/bindings hierarchy as well. OK. > > index 0000000..d766493 > > --- /dev/null > > +++ b/arch/arm64/include/asm/setup.h > > @@ -0,0 +1,26 @@ > > +/* > > + * Based on arch/arm/include/asm/setup.h > > + * > > + * Copyright (C) 1997-1999 Russell King > > + * Copyright (C) 2012 ARM Ltd. > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > > + */ > > +#ifndef __ASM_SETUP_H > > +#define __ASM_SETUP_H > > + > > +#include <linux/types.h> > > + > > +#define COMMAND_LINE_SIZE 1024 > > Probably not a huge deal, and other architectures seem to be all over > the map on this, but you might want to go with a larger value now rather > than later. 2048 or 4096 perhaps? It looks like there are many different values, including the asm-generic one which is 512. I'm happy to follow the x86 example and change it to 2048, it doesn't really matter. > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > > new file mode 100644 > > index 0000000..34ccdc0 > > --- /dev/null > > +++ b/arch/arm64/kernel/head.S > > [...] > > > +/* > > + * Setup common bits before finally enabling the MMU. Essentially this is just > > + * loading the page table pointer and vector base registers. > > + * > > + * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on > > + * the MMU. > > + */ > > +__enable_mmu: > > ENTRY()? __enable_mmu is not used outside this file, so no need for ENTRY(). > > + ldr x5, =vectors > > + msr vbar_el1, x5 > > + msr ttbr0_el1, x25 // load TTBR0 > > + msr ttbr1_el1, x26 // load TTBR1 > > + isb > > + b __turn_mmu_on > > +ENDPROC(__enable_mmu) > > ...or just END()? Same for a few of the other functions below. ENDPROC() gives us ".type @function" in addition to END(). This proved to be useful in the past for debugging symbols, unwind table (though we don't have the latter on AArch64). > > diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c > > new file mode 100644 > > index 0000000..f25186f > > --- /dev/null > > +++ b/arch/arm64/kernel/setup.c > > [...] > > > +static void __init setup_processor(void) > > +{ > > + struct proc_info_list *list; > > + > > + /* > > + * locate processor in the list of supported processor > > + * types. The linker builds this table for us from the > > + * entries in arch/arm/mm/proc.S > > + */ > > Probably from arch/arm64/... somewhere? Yes, I did a grep and found a few more. > > + printk("CPU: %s [%08x] revision %d\n", > > + cpu_name, read_cpuid_id(), read_cpuid_id() & 15); > > + > > + sprintf(init_utsname()->machine, "aarch64"); > > > + initial_boot_params = devtree; > > + dt_root = of_get_flat_dt_root(); > > + > > + machine_name = of_get_flat_dt_prop(dt_root, "model", NULL); > > + if (!machine_name) > > + machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL); > > + if (!machine_name) > > + machine_name = "<unknown>"; > > + pr_info("Machine: %s\n", machine_name); > > This property is an array of strings. It would be more valuable to print out > the entry that was matched for a platform instead of the provided one from the > device tree. If we add machine_desc structure back, we could print which machine was matched. But so far I try to keep the SoC code to a minimum and just do the probing later in the SoC code (of_find_matching_node). Ideally we shouldn't have any SoC code and just keep code in drivers but we'll see how far we can get. We can discuss more details at the KS as I would like the arm-soc team to get involved here. Thanks. -- Catalin
WARNING: multiple messages have this Message-ID (diff)
From: catalin.marinas@arm.com (Catalin Marinas) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 02/31] arm64: Kernel booting and initialisation Date: Wed, 15 Aug 2012 18:37:11 +0100 [thread overview] Message-ID: <20120815173711.GC14264@arm.com> (raw) In-Reply-To: <20120814230645.GA19607@quad.lixom.net> Hi Olof, On Wed, Aug 15, 2012 at 12:06:45AM +0100, Olof Johansson wrote: > On Tue, Aug 14, 2012 at 06:52:03PM +0100, Catalin Marinas wrote: > > +Before jumping into the kernel, the following conditions must be met: > > + > > +- Quiesce all DMA capable devices so that memory does not get > > + corrupted by bogus network packets or disk data. This will save > > + you many hours of debug. > > + > > +- Primary CPU general-purpose register settings > > + x0 = physical address of device tree blob (dtb) in system RAM. > > + > > +- CPU mode > > + All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError, > > + IRQ and FIQ). > > + The CPU must be in either EL2 (RECOMMENDED in order to have access to > > + the virtualisation extensions) or non-secure EL1. > > + > > +- Caches, MMUs > > + The MMU must be off. > > + Instruction cache may be on or off. > > + Data cache must be off and invalidated. > > + > > +- Architected timers > > + CNTFRQ must be programmed with the timer frequency. > > + If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) > > + set where available. > > + > > +- Coherency > > + All CPUs to be booted by the kernel must be part of the same coherency > > + domain on entry to the kernel. This may require IMPLEMENTATION DEFINED > > + initialisation to enable the receiving of maintenance operations on > > + each CPU. > > + > > +- System registers > > + All writable architected system registers at the exception level where > > + the kernel image will be entered must be initialised by software at a > > + higher exception level to prevent execution in an UNKNOWN state. > > Given the recent development of ARM platforms, you might want to mandate > the state of IOMMUs as well (they should probably be off, since there > should be no active DMA activity). Graphics would be the exception to > this, since if you want to keep scanning out a splash screen, you'll > have to keep doing DMA... We'll enhance this document as we get hardware as it's not clear whether we can simply mandate it to be off. We may have situations with some simple IOMMU that is previously set up by the firmware and the kernel doesn't get access to it. One example is the System MMU from ARM that supports stage 2 (hypervisor) translations and you just run a guest kernel without any control of the IOMMU. > > +- The primary CPU must jump directly to the first instruction of the > > + kernel image. The device tree blob passed by this CPU must contain > > + for each CPU node: > > + > > + 1. An 'enable-method' property. Currently, the only supported value > > + for this field is the string "spin-table". > > + > > + 2. A 'cpu-release-addr' property identifying a 64-bit, > > + zero-initialised memory location. > > These would be good to have documented in the > Documentation/devicetree/bindings hierarchy as well. OK. > > index 0000000..d766493 > > --- /dev/null > > +++ b/arch/arm64/include/asm/setup.h > > @@ -0,0 +1,26 @@ > > +/* > > + * Based on arch/arm/include/asm/setup.h > > + * > > + * Copyright (C) 1997-1999 Russell King > > + * Copyright (C) 2012 ARM Ltd. > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License version 2 as > > + * published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope that it will be useful, > > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > + * GNU General Public License for more details. > > + * > > + * You should have received a copy of the GNU General Public License > > + * along with this program. If not, see <http://www.gnu.org/licenses/>. > > + */ > > +#ifndef __ASM_SETUP_H > > +#define __ASM_SETUP_H > > + > > +#include <linux/types.h> > > + > > +#define COMMAND_LINE_SIZE 1024 > > Probably not a huge deal, and other architectures seem to be all over > the map on this, but you might want to go with a larger value now rather > than later. 2048 or 4096 perhaps? It looks like there are many different values, including the asm-generic one which is 512. I'm happy to follow the x86 example and change it to 2048, it doesn't really matter. > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > > new file mode 100644 > > index 0000000..34ccdc0 > > --- /dev/null > > +++ b/arch/arm64/kernel/head.S > > [...] > > > +/* > > + * Setup common bits before finally enabling the MMU. Essentially this is just > > + * loading the page table pointer and vector base registers. > > + * > > + * On entry to this code, x0 must contain the SCTLR_EL1 value for turning on > > + * the MMU. > > + */ > > +__enable_mmu: > > ENTRY()? __enable_mmu is not used outside this file, so no need for ENTRY(). > > + ldr x5, =vectors > > + msr vbar_el1, x5 > > + msr ttbr0_el1, x25 // load TTBR0 > > + msr ttbr1_el1, x26 // load TTBR1 > > + isb > > + b __turn_mmu_on > > +ENDPROC(__enable_mmu) > > ...or just END()? Same for a few of the other functions below. ENDPROC() gives us ".type @function" in addition to END(). This proved to be useful in the past for debugging symbols, unwind table (though we don't have the latter on AArch64). > > diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c > > new file mode 100644 > > index 0000000..f25186f > > --- /dev/null > > +++ b/arch/arm64/kernel/setup.c > > [...] > > > +static void __init setup_processor(void) > > +{ > > + struct proc_info_list *list; > > + > > + /* > > + * locate processor in the list of supported processor > > + * types. The linker builds this table for us from the > > + * entries in arch/arm/mm/proc.S > > + */ > > Probably from arch/arm64/... somewhere? Yes, I did a grep and found a few more. > > + printk("CPU: %s [%08x] revision %d\n", > > + cpu_name, read_cpuid_id(), read_cpuid_id() & 15); > > + > > + sprintf(init_utsname()->machine, "aarch64"); > > > + initial_boot_params = devtree; > > + dt_root = of_get_flat_dt_root(); > > + > > + machine_name = of_get_flat_dt_prop(dt_root, "model", NULL); > > + if (!machine_name) > > + machine_name = of_get_flat_dt_prop(dt_root, "compatible", NULL); > > + if (!machine_name) > > + machine_name = "<unknown>"; > > + pr_info("Machine: %s\n", machine_name); > > This property is an array of strings. It would be more valuable to print out > the entry that was matched for a platform instead of the provided one from the > device tree. If we add machine_desc structure back, we could print which machine was matched. But so far I try to keep the SoC code to a minimum and just do the probing later in the SoC code (of_find_matching_node). Ideally we shouldn't have any SoC code and just keep code in drivers but we'll see how far we can get. We can discuss more details at the KS as I would like the arm-soc team to get involved here. Thanks. -- Catalin
next prev parent reply other threads:[~2012-08-15 17:37 UTC|newest] Thread overview: 442+ messages / expand[flat|nested] mbox.gz Atom feed top 2012-08-14 17:52 [PATCH v2 00/31] AArch64 Linux kernel port Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 01/31] arm64: Assembly macros and definitions Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 12:57 ` Arnd Bergmann 2012-08-15 12:57 ` Arnd Bergmann 2012-08-14 17:52 ` [PATCH v2 02/31] arm64: Kernel booting and initialisation Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 23:06 ` Olof Johansson 2012-08-14 23:06 ` Olof Johansson 2012-08-15 17:37 ` Catalin Marinas [this message] 2012-08-15 17:37 ` Catalin Marinas 2012-08-15 17:37 ` Catalin Marinas 2012-08-15 19:03 ` Olof Johansson 2012-08-15 19:03 ` Olof Johansson 2012-08-15 19:03 ` Olof Johansson 2012-08-15 19:03 ` Olof Johansson 2012-08-15 19:53 ` Catalin Marinas 2012-08-15 19:53 ` Catalin Marinas 2012-08-15 19:53 ` Catalin Marinas 2012-08-15 19:53 ` Catalin Marinas 2012-08-15 13:20 ` Arnd Bergmann 2012-08-15 13:20 ` Arnd Bergmann 2012-08-15 17:06 ` Olof Johansson 2012-08-15 17:06 ` Olof Johansson 2012-08-16 12:53 ` Catalin Marinas 2012-08-16 12:53 ` Catalin Marinas 2012-08-16 12:53 ` Catalin Marinas 2012-08-16 18:59 ` Nicolas Pitre 2012-08-16 18:59 ` Nicolas Pitre 2012-08-17 11:20 ` Arnd Bergmann 2012-08-17 11:20 ` Arnd Bergmann 2012-08-17 13:45 ` Catalin Marinas 2012-08-17 13:45 ` Catalin Marinas 2012-08-17 13:45 ` Catalin Marinas 2012-08-17 18:21 ` Nicolas Pitre 2012-08-17 18:21 ` Nicolas Pitre 2012-08-17 8:56 ` Tony Lindgren 2012-08-17 8:56 ` Tony Lindgren 2012-08-17 9:41 ` Santosh Shilimkar 2012-08-17 9:41 ` Santosh Shilimkar 2012-08-17 10:05 ` Catalin Marinas 2012-08-17 10:05 ` Catalin Marinas 2012-08-17 10:05 ` Catalin Marinas 2012-08-17 10:05 ` Catalin Marinas 2012-08-17 10:10 ` Shilimkar, Santosh 2012-08-17 10:10 ` Shilimkar, Santosh 2012-08-17 10:10 ` Shilimkar, Santosh 2012-08-17 13:13 ` Tony Lindgren 2012-08-17 13:13 ` Tony Lindgren 2012-08-17 13:13 ` Tony Lindgren 2012-08-17 13:48 ` Catalin Marinas 2012-08-17 13:48 ` Catalin Marinas 2012-08-17 13:48 ` Catalin Marinas 2012-08-24 9:50 ` Catalin Marinas 2012-08-24 9:50 ` Catalin Marinas 2012-08-24 9:50 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 03/31] arm64: Exception handling Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 23:29 ` Olof Johansson 2012-08-14 23:29 ` Olof Johansson 2012-08-14 23:47 ` Thomas Gleixner 2012-08-14 23:47 ` Thomas Gleixner 2012-08-15 13:03 ` Arnd Bergmann 2012-08-15 13:03 ` Arnd Bergmann 2012-08-16 10:05 ` Will Deacon 2012-08-16 10:05 ` Will Deacon 2012-08-16 10:05 ` Will Deacon 2012-08-16 10:05 ` Will Deacon 2012-08-16 11:54 ` Arnd Bergmann 2012-08-16 11:54 ` Arnd Bergmann 2012-08-16 11:54 ` Arnd Bergmann 2012-08-14 17:52 ` [PATCH v2 04/31] arm64: MMU definitions Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 13:30 ` Arnd Bergmann 2012-08-15 13:30 ` Arnd Bergmann 2012-08-15 13:39 ` Catalin Marinas 2012-08-15 13:39 ` Catalin Marinas 2012-08-15 13:39 ` Catalin Marinas 2012-08-15 16:34 ` Geert Uytterhoeven 2012-08-15 16:34 ` Geert Uytterhoeven 2012-08-15 16:45 ` Catalin Marinas 2012-08-15 16:45 ` Catalin Marinas 2012-08-15 16:45 ` Catalin Marinas 2012-08-17 9:04 ` Tony Lindgren 2012-08-17 9:04 ` Tony Lindgren 2012-08-17 9:21 ` Catalin Marinas 2012-08-17 9:21 ` Catalin Marinas 2012-08-17 9:21 ` Catalin Marinas 2012-08-17 9:38 ` Tony Lindgren 2012-08-17 9:38 ` Tony Lindgren 2012-08-17 9:38 ` Tony Lindgren 2012-08-14 17:52 ` [PATCH v2 05/31] arm64: MMU initialisation Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 13:45 ` Arnd Bergmann 2012-08-15 13:45 ` Arnd Bergmann 2012-08-17 10:06 ` Santosh Shilimkar 2012-08-17 10:06 ` Santosh Shilimkar 2012-08-17 10:15 ` Catalin Marinas 2012-08-17 10:15 ` Catalin Marinas 2012-08-17 10:15 ` Catalin Marinas 2012-08-17 10:25 ` Shilimkar, Santosh 2012-08-17 10:25 ` Shilimkar, Santosh 2012-08-17 10:25 ` Shilimkar, Santosh 2012-08-14 17:52 ` [PATCH v2 06/31] arm64: MMU fault handling and page table management Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 13:47 ` Arnd Bergmann 2012-08-15 13:47 ` Arnd Bergmann 2012-08-17 16:07 ` Catalin Marinas 2012-08-17 16:07 ` Catalin Marinas 2012-08-17 16:07 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 07/31] arm64: Process management Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 23:50 ` Olof Johansson 2012-08-14 23:50 ` Olof Johansson 2012-09-14 17:33 ` Catalin Marinas 2012-09-14 17:33 ` Catalin Marinas 2012-09-14 17:33 ` Catalin Marinas 2012-09-16 0:29 ` Olof Johansson 2012-09-16 0:29 ` Olof Johansson 2012-09-16 0:29 ` Olof Johansson 2012-08-15 13:53 ` Arnd Bergmann 2012-08-15 13:53 ` Arnd Bergmann 2012-08-17 16:15 ` Catalin Marinas 2012-08-17 16:15 ` Catalin Marinas 2012-08-17 16:15 ` Catalin Marinas 2012-08-16 15:09 ` Tobias Klauser 2012-08-16 15:09 ` Tobias Klauser 2012-08-14 17:52 ` [PATCH v2 08/31] arm64: CPU support Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 0:10 ` Olof Johansson 2012-08-15 0:10 ` Olof Johansson 2012-08-20 15:57 ` Catalin Marinas 2012-08-20 15:57 ` Catalin Marinas 2012-08-20 15:57 ` Catalin Marinas 2012-08-20 20:47 ` Arnd Bergmann 2012-08-20 20:47 ` Arnd Bergmann 2012-08-20 20:47 ` Arnd Bergmann 2012-08-21 9:50 ` Catalin Marinas 2012-08-21 9:50 ` Catalin Marinas 2012-08-21 9:50 ` Catalin Marinas 2012-09-14 17:38 ` Catalin Marinas 2012-09-14 17:38 ` Catalin Marinas 2012-09-14 17:38 ` Catalin Marinas 2012-08-15 13:56 ` Arnd Bergmann 2012-08-15 13:56 ` Arnd Bergmann 2012-08-20 16:00 ` Catalin Marinas 2012-08-20 16:00 ` Catalin Marinas 2012-08-20 16:00 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 09/31] arm64: Cache maintenance routines Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-17 9:57 ` Santosh Shilimkar 2012-08-17 9:57 ` Santosh Shilimkar 2012-08-17 9:57 ` Santosh Shilimkar 2012-08-17 10:07 ` Catalin Marinas 2012-08-17 10:07 ` Catalin Marinas 2012-08-17 10:07 ` Catalin Marinas 2012-08-17 10:12 ` Shilimkar, Santosh 2012-08-17 10:12 ` Shilimkar, Santosh 2012-08-17 10:12 ` Shilimkar, Santosh 2012-08-14 17:52 ` [PATCH v2 10/31] arm64: TLB maintenance functionality Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 11/31] arm64: IRQ handling Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 23:22 ` Aaro Koskinen 2012-08-14 23:22 ` Aaro Koskinen 2012-08-14 17:52 ` [PATCH v2 12/31] arm64: Atomic operations Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 0:21 ` Olof Johansson 2012-08-15 0:21 ` Olof Johansson 2012-08-14 17:52 ` [PATCH v2 13/31] arm64: Device specific operations Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 0:33 ` Olof Johansson 2012-08-15 0:33 ` Olof Johansson 2012-09-14 17:29 ` Catalin Marinas 2012-09-14 17:29 ` Catalin Marinas 2012-09-14 17:29 ` Catalin Marinas 2012-09-14 17:31 ` Arnd Bergmann 2012-09-14 17:31 ` Arnd Bergmann 2012-09-14 17:31 ` Arnd Bergmann 2012-09-14 17:39 ` Catalin Marinas 2012-09-14 17:39 ` Catalin Marinas 2012-09-14 17:39 ` Catalin Marinas 2012-09-16 0:28 ` Olof Johansson 2012-09-16 0:28 ` Olof Johansson 2012-09-16 0:28 ` Olof Johansson 2012-08-15 16:13 ` Arnd Bergmann 2012-08-15 16:13 ` Arnd Bergmann 2012-08-17 9:19 ` Tony Lindgren 2012-08-17 9:19 ` Tony Lindgren 2012-08-17 9:19 ` Tony Lindgren 2012-08-14 17:52 ` [PATCH v2 14/31] arm64: DMA mapping API Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 0:40 ` Olof Johansson 2012-08-15 0:40 ` Olof Johansson 2012-08-15 0:40 ` Olof Johansson 2012-08-21 13:05 ` Catalin Marinas 2012-08-21 13:05 ` Catalin Marinas 2012-08-21 13:05 ` Catalin Marinas 2012-08-15 16:16 ` Arnd Bergmann 2012-08-15 16:16 ` Arnd Bergmann 2012-08-21 12:59 ` Catalin Marinas 2012-08-21 12:59 ` Catalin Marinas 2012-08-21 12:59 ` Catalin Marinas 2012-08-21 12:59 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 15/31] arm64: SMP support Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 0:49 ` Olof Johansson 2012-08-15 0:49 ` Olof Johansson 2012-08-15 13:04 ` Arnd Bergmann 2012-08-15 13:04 ` Arnd Bergmann 2012-08-17 9:21 ` Tony Lindgren 2012-08-17 9:21 ` Tony Lindgren 2012-08-17 9:32 ` Catalin Marinas 2012-08-17 9:32 ` Catalin Marinas 2012-08-17 9:32 ` Catalin Marinas 2012-08-17 9:39 ` Tony Lindgren 2012-08-17 9:39 ` Tony Lindgren 2012-08-17 9:39 ` Tony Lindgren 2012-08-14 17:52 ` [PATCH v2 16/31] arm64: ELF definitions Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 14:15 ` Arnd Bergmann 2012-08-15 14:15 ` Arnd Bergmann 2012-08-16 10:23 ` Will Deacon 2012-08-16 10:23 ` Will Deacon 2012-08-16 10:23 ` Will Deacon 2012-08-16 10:23 ` Will Deacon 2012-08-16 12:37 ` Arnd Bergmann 2012-08-16 12:37 ` Arnd Bergmann 2012-08-16 12:37 ` Arnd Bergmann 2012-08-21 16:06 ` Catalin Marinas 2012-08-21 16:06 ` Catalin Marinas 2012-08-21 16:06 ` Catalin Marinas 2012-08-21 18:17 ` Geert Uytterhoeven 2012-08-21 18:17 ` Geert Uytterhoeven 2012-08-21 18:17 ` Geert Uytterhoeven 2012-08-21 18:17 ` Geert Uytterhoeven 2012-08-21 18:27 ` Catalin Marinas 2012-08-21 18:27 ` Catalin Marinas 2012-08-21 18:27 ` Catalin Marinas 2012-08-21 18:53 ` Mike Frysinger 2012-08-21 18:53 ` Mike Frysinger 2012-08-21 18:53 ` Mike Frysinger 2012-08-21 20:17 ` Arnd Bergmann 2012-08-21 20:17 ` Arnd Bergmann 2012-08-21 20:17 ` Arnd Bergmann 2012-09-05 19:56 ` Chris Metcalf 2012-09-05 19:56 ` Chris Metcalf 2012-09-05 19:56 ` Chris Metcalf 2012-08-14 17:52 ` [PATCH v2 17/31] arm64: System calls handling Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 14:22 ` Arnd Bergmann 2012-08-15 14:22 ` Arnd Bergmann 2012-08-21 17:51 ` Catalin Marinas 2012-08-21 17:51 ` Catalin Marinas 2012-08-21 17:51 ` Catalin Marinas 2012-08-21 20:14 ` Arnd Bergmann 2012-08-21 20:14 ` Arnd Bergmann 2012-08-21 20:14 ` Arnd Bergmann 2012-08-21 20:14 ` Arnd Bergmann 2012-08-21 22:01 ` Catalin Marinas 2012-08-21 22:01 ` Catalin Marinas 2012-08-21 22:01 ` Catalin Marinas 2012-08-22 7:56 ` Arnd Bergmann 2012-08-22 7:56 ` Arnd Bergmann 2012-08-22 7:56 ` Arnd Bergmann 2012-08-22 10:29 ` Catalin Marinas 2012-08-22 10:29 ` Catalin Marinas 2012-08-22 10:29 ` Catalin Marinas 2012-08-22 12:27 ` Arnd Bergmann 2012-08-22 12:27 ` Arnd Bergmann 2012-08-22 12:27 ` Arnd Bergmann 2012-08-22 17:13 ` Catalin Marinas 2012-08-22 17:13 ` Catalin Marinas 2012-08-22 17:13 ` Catalin Marinas 2012-09-03 11:48 ` Catalin Marinas 2012-09-03 11:48 ` Catalin Marinas 2012-09-03 11:48 ` Catalin Marinas 2012-09-03 12:39 ` Arnd Bergmann 2012-09-03 12:39 ` Arnd Bergmann 2012-09-03 12:39 ` Arnd Bergmann 2012-08-14 17:52 ` [PATCH v2 18/31] arm64: VDSO support Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 19/31] arm64: Signal handling support Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 20/31] arm64: User access library functions Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 14:49 ` [PATCH v2 20/31] arm64: User access library function Arnd Bergmann 2012-08-15 14:49 ` Arnd Bergmann 2012-09-03 12:58 ` Catalin Marinas 2012-09-03 12:58 ` Catalin Marinas 2012-09-03 12:58 ` Catalin Marinas 2012-09-05 19:13 ` Russell King - ARM Linux 2012-09-05 19:13 ` Russell King - ARM Linux 2012-09-05 21:01 ` Catalin Marinas 2012-09-05 21:01 ` Catalin Marinas 2012-09-05 21:01 ` Catalin Marinas 2012-09-05 21:05 ` Russell King - ARM Linux 2012-09-05 21:05 ` Russell King - ARM Linux 2012-09-05 21:05 ` Russell King - ARM Linux 2012-09-06 8:36 ` Catalin Marinas 2012-09-06 8:36 ` Catalin Marinas 2012-09-06 8:36 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 21/31] arm64: 32-bit (compat) applications support Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 14:34 ` Arnd Bergmann 2012-08-15 14:34 ` Arnd Bergmann 2012-08-16 10:28 ` Will Deacon 2012-08-16 10:28 ` Will Deacon 2012-08-16 10:28 ` Will Deacon 2012-08-16 12:39 ` Arnd Bergmann 2012-08-16 12:39 ` Arnd Bergmann 2012-08-16 12:39 ` Arnd Bergmann 2012-08-23 6:46 ` PER_LINUX32, Was: " Arnd Bergmann 2012-08-23 6:46 ` Arnd Bergmann 2012-08-23 6:46 ` Arnd Bergmann 2012-08-23 10:42 ` Catalin Marinas 2012-08-23 10:42 ` Catalin Marinas 2012-08-23 10:42 ` Catalin Marinas 2012-08-28 18:28 ` Jiri Kosina 2012-08-28 18:28 ` Jiri Kosina 2012-08-28 18:28 ` Jiri Kosina 2012-08-24 10:43 ` Catalin Marinas 2012-08-24 10:43 ` Catalin Marinas 2012-08-24 10:43 ` Catalin Marinas 2012-08-26 4:49 ` Arnd Bergmann 2012-08-26 4:49 ` Arnd Bergmann 2012-08-26 4:49 ` Arnd Bergmann 2012-08-26 4:49 ` Arnd Bergmann 2012-08-20 10:53 ` Pavel Machek 2012-08-20 10:53 ` Pavel Machek 2012-08-20 20:34 ` Arnd Bergmann 2012-08-20 20:34 ` Arnd Bergmann 2012-08-21 10:28 ` Pavel Machek 2012-08-21 10:28 ` Pavel Machek 2012-08-14 17:52 ` [PATCH v2 22/31] arm64: Floating point and SIMD Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 14:35 ` Arnd Bergmann 2012-08-15 14:35 ` Arnd Bergmann 2012-08-14 17:52 ` [PATCH v2 23/31] arm64: Debugging support Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 15:07 ` Arnd Bergmann 2012-08-15 15:07 ` Arnd Bergmann 2012-08-15 15:07 ` Arnd Bergmann 2012-08-16 10:47 ` Will Deacon 2012-08-16 10:47 ` Will Deacon 2012-08-16 10:47 ` Will Deacon 2012-08-16 12:49 ` Arnd Bergmann 2012-08-16 12:49 ` Arnd Bergmann 2012-08-16 12:49 ` Arnd Bergmann 2012-08-17 7:06 ` Arnd Bergmann 2012-08-17 7:06 ` Arnd Bergmann 2012-08-17 7:06 ` Arnd Bergmann 2012-08-20 9:07 ` Will Deacon 2012-08-20 9:07 ` Will Deacon 2012-08-20 9:07 ` Will Deacon 2012-08-20 9:27 ` Will Deacon 2012-08-20 9:27 ` Will Deacon 2012-08-20 9:27 ` Will Deacon 2012-08-20 20:10 ` Arnd Bergmann 2012-08-20 20:10 ` Arnd Bergmann 2012-08-20 20:10 ` Arnd Bergmann 2012-08-21 8:58 ` Will Deacon 2012-08-21 8:58 ` Will Deacon 2012-08-21 8:58 ` Will Deacon 2012-08-21 8:58 ` Will Deacon 2012-08-14 17:52 ` [PATCH v2 24/31] arm64: Add support for /proc/sys/debug/exception-trace Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 15:08 ` Arnd Bergmann 2012-08-15 15:08 ` Arnd Bergmann 2012-08-14 17:52 ` [PATCH v2 25/31] arm64: Performance counters support Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 15:11 ` Arnd Bergmann 2012-08-15 15:11 ` Arnd Bergmann 2012-08-16 10:51 ` Will Deacon 2012-08-16 10:51 ` Will Deacon 2012-08-16 10:51 ` Will Deacon 2012-08-14 17:52 ` [PATCH v2 26/31] arm64: Miscellaneous library functions Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 15:21 ` Arnd Bergmann 2012-08-15 15:21 ` Arnd Bergmann 2012-08-16 10:57 ` Will Deacon 2012-08-16 10:57 ` Will Deacon 2012-08-16 10:57 ` Will Deacon 2012-08-16 13:00 ` Arnd Bergmann 2012-08-16 13:00 ` Arnd Bergmann 2012-08-16 13:00 ` Arnd Bergmann 2012-08-16 14:11 ` Catalin Marinas 2012-08-16 14:11 ` Catalin Marinas 2012-08-16 14:11 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 27/31] arm64: Loadable modules Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 15:23 ` Arnd Bergmann 2012-08-15 15:23 ` Arnd Bergmann 2012-08-15 15:35 ` Catalin Marinas 2012-08-15 15:35 ` Catalin Marinas 2012-08-15 15:35 ` Catalin Marinas 2012-08-15 16:16 ` Arnd Bergmann 2012-08-15 16:16 ` Arnd Bergmann 2012-08-15 16:16 ` Arnd Bergmann 2012-08-14 17:52 ` [PATCH v2 28/31] arm64: Generic timers support Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 15:52 ` Arnd Bergmann 2012-08-15 15:52 ` Arnd Bergmann 2012-08-16 12:40 ` Linus Walleij 2012-08-16 12:40 ` Linus Walleij 2012-08-17 9:29 ` Tony Lindgren 2012-08-17 9:29 ` Tony Lindgren 2012-08-17 10:21 ` Santosh Shilimkar 2012-08-17 10:21 ` Santosh Shilimkar 2012-08-21 19:20 ` Christopher Covington 2012-08-21 19:20 ` Christopher Covington 2012-08-14 17:52 ` [PATCH v2 29/31] arm64: Miscellaneous header files Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 15:56 ` Arnd Bergmann 2012-08-15 15:56 ` Arnd Bergmann 2012-08-14 17:52 ` [PATCH v2 30/31] arm64: Build infrastructure Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-14 21:01 ` Sam Ravnborg 2012-08-14 21:01 ` Sam Ravnborg 2012-08-15 16:07 ` Arnd Bergmann 2012-08-15 16:07 ` Arnd Bergmann 2012-08-17 9:32 ` Tony Lindgren 2012-08-17 9:32 ` Tony Lindgren 2012-08-17 9:46 ` Catalin Marinas 2012-08-17 9:46 ` Catalin Marinas 2012-08-17 9:46 ` Catalin Marinas 2012-08-14 17:52 ` [PATCH v2 31/31] arm64: MAINTAINERS update Catalin Marinas 2012-08-14 17:52 ` Catalin Marinas 2012-08-15 15:57 ` Arnd Bergmann 2012-08-15 15:57 ` Arnd Bergmann 2012-08-17 9:36 ` [PATCH v2 00/31] AArch64 Linux kernel port Tony Lindgren 2012-08-17 9:36 ` Tony Lindgren
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20120815173711.GC14264@arm.com \ --to=catalin.marinas@arm.com \ --cc=Will.Deacon@arm.com \ --cc=arnd@arndb.de \ --cc=linux-arch@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=olof@lixom.net \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.