linux-next: manual merge of the drm-intel tree with the drm-intel-fixes tree

From: Stephen Rothwell <sfr@canb.auug.org.au>
To: Daniel Vetter <daniel.vetter@ffwll.ch>,
	<intel-gfx@lists.freedesktop.org>,
	<dri-devel@lists.freedesktop.org>
Cc: linux-next@vger.kernel.org, linux-kernel@vger.kernel.org,
	Chris Wilson <chris@chris-wilson.co.uk>,
	Ben Widawsky <ben@bwidawsk.net>
Subject: linux-next: manual merge of the drm-intel tree with the drm-intel-fixes tree
Date: Tue, 16 Jul 2013 12:05:23 +1000	[thread overview]
Message-ID: <20130716120523.32e132972134f55a0655d3c9@canb.auug.org.au> (raw)

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Hi all,

Today's linux-next merge of the drm-intel tree got a conflict in
drivers/gpu/drm/i915/i915_gem.c between commits 19b2dbde5732
("drm/i915: Restore fences after resume and GPU resets") from Linus' tree
and d18b96190342 ("drm/i915: Fix incoherence with fence updates on
Sandybridge+") from the drm-intel-fixes tree and commits f343c5f64773
("drm/i915: Getter/setter for object attributes") and db1b76ca6a79
("drm/i915: don't frob mm.suspended when not using ums") from the
drm-intel tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@canb.auug.org.au

diff --cc drivers/gpu/drm/i915/i915_gem.c
index 97afd26,20b10a0..0000000

--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@@ -2666,27 -2673,12 +2665,27 @@@ static void i965_write_fence_reg(struc
  		fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
  	}
  
 +	fence_reg += reg * 8;
 +
 +	/* To w/a incoherency with non-atomic 64-bit register updates,
 +	 * we split the 64-bit update into two 32-bit writes. In order
 +	 * for a partial fence not to be evaluated between writes, we
 +	 * precede the update with write to turn off the fence register,
 +	 * and only enable the fence as the last step.
 +	 *
 +	 * For extra levels of paranoia, we make sure each step lands
 +	 * before applying the next step.
 +	 */
 +	I915_WRITE(fence_reg, 0);
 +	POSTING_READ(fence_reg);
 +
  	if (obj) {
- 		u32 size = obj->gtt_space->size;
+ 		u32 size = i915_gem_obj_ggtt_size(obj);
 +		uint64_t val;
  
- 		val = (uint64_t)((obj->gtt_offset + size - 4096) &
+ 		val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
  				 0xfffff000) << 32;
- 		val |= obj->gtt_offset & 0xfffff000;
+ 		val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
  		val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
  		if (obj->tiling_mode == I915_TILING_Y)
  			val |= 1 << I965_FENCE_TILING_Y_SHIFT;
@@@ -3992,11 -4008,8 +3980,6 @@@ i915_gem_idle(struct drm_device *dev
  	if (!drm_core_check_feature(dev, DRIVER_MODESET))
  		i915_gem_evict_everything(dev);
  
- 	/* Hack!  Don't let anybody do execbuf while we don't control the chip.
- 	 * We need to replace this with a semaphore, or something.
- 	 * And not confound mm.suspended!
- 	 */
- 	dev_priv->mm.suspended = 1;
 -	i915_gem_reset_fences(dev);
 -
  	del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
  
  	i915_kernel_lost_context(dev);

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