From: Wolfram Sang <wsa@the-dreams.de>
To: Addy Ke <addy.ke@rock-chips.com>
Cc: max.schwarz@online.de, heiko@sntech.de, olof@lixom.net,
dianders@chromium.org, linux-i2c@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, cf@rock-chips.com,
xjq@rock-chips.com, huangtao@rock-chips.com, zyw@rock-chips.com,
yzq@rock-chips.com, hj@rock-chips.com, kever.yang@rock-chips.com,
hl@rock-chips.com, caesar.wang@rock-chips.com,
zhengsq@rock-chips.com
Subject: Re: [PATCH v6] i2c: rk3x: adjust the LOW divison based on characteristics of SCL
Date: Mon, 10 Nov 2014 15:58:52 +0100 [thread overview]
Message-ID: <20141110145852.GD10422@katana> (raw)
In-Reply-To: <1413266961-3859-1-git-send-email-addy.ke@rock-chips.com>
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On Tue, Oct 14, 2014 at 02:09:21PM +0800, Addy Ke wrote:
> As show in I2C specification:
> - Standard-mode: the minimum HIGH period of the scl clock is 4.0us
> the minimum LOW period of the scl clock is 4.7us
> - Fast-mode: the minimum HIGH period of the scl clock is 0.6us
> the minimum LOW period of the scl clock is 1.3us
>
> I have measured i2c SCL waveforms in fast-mode by oscilloscope
> on rk3288-pinky board. the LOW period of the scl clock is 1.3us.
> It is so critical that we must adjust LOW division to increase
> the LOW period of the scl clock.
>
> Thanks Doug for the suggestion about division formulas.
>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Applied to for-next, thanks!
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From: Wolfram Sang <wsa-z923LK4zBo2bacvFa/9K2g@public.gmane.org>
To: Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Cc: max.schwarz-BGeptl67XyCzQB+pC5nmwQ@public.gmane.org,
heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org,
olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org,
dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
cf-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
xjq-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
zyw-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
yzq-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
hj-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
kever.yang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
caesar.wang-TNX95d0MmH7DzftRWevZcw@public.gmane.org,
zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org
Subject: Re: [PATCH v6] i2c: rk3x: adjust the LOW divison based on characteristics of SCL
Date: Mon, 10 Nov 2014 15:58:52 +0100 [thread overview]
Message-ID: <20141110145852.GD10422@katana> (raw)
In-Reply-To: <1413266961-3859-1-git-send-email-addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
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On Tue, Oct 14, 2014 at 02:09:21PM +0800, Addy Ke wrote:
> As show in I2C specification:
> - Standard-mode: the minimum HIGH period of the scl clock is 4.0us
> the minimum LOW period of the scl clock is 4.7us
> - Fast-mode: the minimum HIGH period of the scl clock is 0.6us
> the minimum LOW period of the scl clock is 1.3us
>
> I have measured i2c SCL waveforms in fast-mode by oscilloscope
> on rk3288-pinky board. the LOW period of the scl clock is 1.3us.
> It is so critical that we must adjust LOW division to increase
> the LOW period of the scl clock.
>
> Thanks Doug for the suggestion about division formulas.
>
> Tested-by: Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
> Reviewed-by: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Tested-by: Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Signed-off-by: Addy Ke <addy.ke-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Applied to for-next, thanks!
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WARNING: multiple messages have this Message-ID (diff)
From: wsa@the-dreams.de (Wolfram Sang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6] i2c: rk3x: adjust the LOW divison based on characteristics of SCL
Date: Mon, 10 Nov 2014 15:58:52 +0100 [thread overview]
Message-ID: <20141110145852.GD10422@katana> (raw)
In-Reply-To: <1413266961-3859-1-git-send-email-addy.ke@rock-chips.com>
On Tue, Oct 14, 2014 at 02:09:21PM +0800, Addy Ke wrote:
> As show in I2C specification:
> - Standard-mode: the minimum HIGH period of the scl clock is 4.0us
> the minimum LOW period of the scl clock is 4.7us
> - Fast-mode: the minimum HIGH period of the scl clock is 0.6us
> the minimum LOW period of the scl clock is 1.3us
>
> I have measured i2c SCL waveforms in fast-mode by oscilloscope
> on rk3288-pinky board. the LOW period of the scl clock is 1.3us.
> It is so critical that we must adjust LOW division to increase
> the LOW period of the scl clock.
>
> Thanks Doug for the suggestion about division formulas.
>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Tested-by: Doug Anderson <dianders@chromium.org>
> Signed-off-by: Addy Ke <addy.ke@rock-chips.com>
Applied to for-next, thanks!
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next prev parent reply other threads:[~2014-11-10 14:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-13 2:44 [PATCH v5] i2c: rk3x: adjust the LOW divison based on characteristics of SCL Addy Ke
2014-10-13 2:44 ` Addy Ke
2014-10-13 8:34 ` Max Schwarz
2014-10-13 8:34 ` Max Schwarz
2014-10-13 8:34 ` Max Schwarz
2014-10-14 6:09 ` [PATCH v6] " Addy Ke
2014-10-14 6:09 ` Addy Ke
2014-10-14 6:09 ` Addy Ke
2014-10-14 22:42 ` Max Schwarz
2014-10-14 22:42 ` Max Schwarz
2014-10-14 22:42 ` Max Schwarz
2014-11-10 14:58 ` Wolfram Sang [this message]
2014-11-10 14:58 ` Wolfram Sang
2014-11-10 14:58 ` Wolfram Sang
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