From: Nicolin Chen <nicoleotsuka@gmail.com> To: Zidan Wang <b50113@freescale.com> Cc: Zidan Wang <zidan.wang@freescale.com>, timur@tabi.org, Xiubo.Lee@gmail.com, lgirdwood@gmail.com, broonie@kernel.org, perex@perex.cz, tiwai@suse.de, alsa-devel@alsa-project.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: Re: [alsa-devel][PATCH 1/3] SoC: fsl_sai: add sai master mode support Date: Wed, 21 Jan 2015 09:36:21 -0800 [thread overview] Message-ID: <20150121173619.GA1184@Asurada> (raw) In-Reply-To: <20150121092529.GA27441@b50113> On Wed, Jan 21, 2015 at 05:25:32PM +0800, Zidan Wang wrote: > On Tue, Jan 20, 2015 at 10:07:03PM -0800, Nicolin Chen wrote: > > On Tue, Jan 20, 2015 at 08:21:18PM +0800, Zidan Wang wrote: > > > + if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) { > > > + regmap_update_bits(sai->regmap, FSL_SAI_RCR2, > > > + FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai->mclk_id)); > > "tx && sai->synchronous[TX]" means the playback in synchronous > > mode (TX following RX). What if the recording has been already > > activated with an MSEL setting at this point? Then the playback > > stream, as a secondary stream, will overwrite MSEL of the first > > stream -- Record. Same would happen to the DIV configuration. > > > When TX following RX(or RX following TX), TX and RX works on same bit > clock and frame clock. They will use same MCLK source, and just need set > the bclk DIV for RX(or TX). The secondary stream will overwrite MSEL and > bclk DIV of the first stream, but it doesn't matter. > > For RX(or TX) sync: > fsl_sai_dai.symmetric_rates = 1; > fsl_sai_dai.symmetric_channels = 1; > fsl_sai_dai.symmetric_samplebits = 1; Ah, I forgot we have protection here. It's fine then. > When TX and RX both works on async mode, TX and RX may works on > different bit clock and frame clock. We need set MCLK source and bclk > DIV for TX and RX. mclk_id just save a MCLK source id, so i need to define > mclk_id[2] for differnet stream. Yes, you need to change this part as you just realized. And one more thing for your coding style for multi-line comment: /* * Typically use this format. */ Thanks Nicolin
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicoleotsuka@gmail.com> To: Zidan Wang <b50113@freescale.com> Cc: alsa-devel@alsa-project.org, timur@tabi.org, Zidan Wang <zidan.wang@freescale.com>, Xiubo.Lee@gmail.com, tiwai@suse.de, linux-kernel@vger.kernel.org, lgirdwood@gmail.com, perex@perex.cz, broonie@kernel.org, linuxppc-dev@lists.ozlabs.org Subject: Re: [alsa-devel][PATCH 1/3] SoC: fsl_sai: add sai master mode support Date: Wed, 21 Jan 2015 09:36:21 -0800 [thread overview] Message-ID: <20150121173619.GA1184@Asurada> (raw) In-Reply-To: <20150121092529.GA27441@b50113> On Wed, Jan 21, 2015 at 05:25:32PM +0800, Zidan Wang wrote: > On Tue, Jan 20, 2015 at 10:07:03PM -0800, Nicolin Chen wrote: > > On Tue, Jan 20, 2015 at 08:21:18PM +0800, Zidan Wang wrote: > > > + if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) { > > > + regmap_update_bits(sai->regmap, FSL_SAI_RCR2, > > > + FSL_SAI_CR2_MSEL_MASK, FSL_SAI_CR2_MSEL(sai->mclk_id)); > > "tx && sai->synchronous[TX]" means the playback in synchronous > > mode (TX following RX). What if the recording has been already > > activated with an MSEL setting at this point? Then the playback > > stream, as a secondary stream, will overwrite MSEL of the first > > stream -- Record. Same would happen to the DIV configuration. > > > When TX following RX(or RX following TX), TX and RX works on same bit > clock and frame clock. They will use same MCLK source, and just need set > the bclk DIV for RX(or TX). The secondary stream will overwrite MSEL and > bclk DIV of the first stream, but it doesn't matter. > > For RX(or TX) sync: > fsl_sai_dai.symmetric_rates = 1; > fsl_sai_dai.symmetric_channels = 1; > fsl_sai_dai.symmetric_samplebits = 1; Ah, I forgot we have protection here. It's fine then. > When TX and RX both works on async mode, TX and RX may works on > different bit clock and frame clock. We need set MCLK source and bclk > DIV for TX and RX. mclk_id just save a MCLK source id, so i need to define > mclk_id[2] for differnet stream. Yes, you need to change this part as you just realized. And one more thing for your coding style for multi-line comment: /* * Typically use this format. */ Thanks Nicolin
next prev parent reply other threads:[~2015-01-21 17:37 UTC|newest] Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-01-20 12:21 [alsa-devel][PATCH 0/3] Add master mode, tmd and right-j mode support Zidan Wang 2015-01-20 12:21 ` Zidan Wang 2015-01-20 12:21 ` [PATCH " Zidan Wang 2015-01-20 12:21 ` [alsa-devel][PATCH 1/3] SoC: fsl_sai: add sai master " Zidan Wang 2015-01-20 12:21 ` Zidan Wang 2015-01-20 12:21 ` Zidan Wang 2015-01-21 6:07 ` Nicolin Chen 2015-01-21 6:07 ` Nicolin Chen 2015-01-21 9:25 ` Zidan Wang 2015-01-21 9:25 ` Zidan Wang 2015-01-21 9:25 ` [PATCH " Zidan Wang 2015-01-21 17:36 ` Nicolin Chen [this message] 2015-01-21 17:36 ` [alsa-devel][PATCH " Nicolin Chen 2015-01-20 12:21 ` [alsa-devel][PATCH 2/3] ASoC: fsl_sai: Add support for tdm slots operation Zidan Wang 2015-01-20 12:21 ` Zidan Wang 2015-01-20 12:21 ` [PATCH " Zidan Wang 2015-01-21 18:08 ` [alsa-devel][PATCH " Nicolin Chen 2015-01-21 18:08 ` Nicolin Chen 2015-01-22 4:55 ` Zidan Wang 2015-01-22 4:55 ` Zidan Wang 2015-01-22 4:55 ` Zidan Wang 2015-01-22 5:44 ` Nicolin Chen 2015-01-22 5:44 ` Nicolin Chen 2015-01-22 6:20 ` Zidan Wang 2015-01-22 6:20 ` Zidan Wang 2015-01-22 6:20 ` Zidan Wang 2015-01-22 23:50 ` Nicolin Chen 2015-01-22 23:50 ` Nicolin Chen 2015-01-23 2:55 ` Zidan Wang 2015-01-23 2:55 ` Zidan Wang 2015-01-23 2:55 ` [PATCH " Zidan Wang 2015-01-23 8:27 ` [alsa-devel][PATCH " Nicolin Chen 2015-01-23 8:27 ` Nicolin Chen 2015-01-20 12:21 ` [alsa-devel][PATCH 3/3] ASoC: fsl_sai: Add support for Right-J mode Zidan Wang 2015-01-20 12:21 ` Zidan Wang 2015-01-20 12:21 ` [PATCH " Zidan Wang 2015-01-21 18:53 ` [alsa-devel][PATCH " Nicolin Chen 2015-01-21 18:53 ` Nicolin Chen 2015-01-22 5:13 ` Zidan Wang 2015-01-22 5:13 ` Zidan Wang 2015-01-22 5:13 ` Zidan Wang 2015-01-22 5:46 ` Nicolin Chen 2015-01-22 5:46 ` Nicolin Chen 2015-01-21 1:15 ` [alsa-devel] [PATCH 0/3] Add master mode, tmd and right-j mode support Fabio Estevam 2015-01-21 1:15 ` Fabio Estevam 2015-01-21 6:29 ` Nicolin Chen 2015-01-21 6:29 ` Nicolin Chen
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