Re: [PATCH v6 02/19] drm/i915/gen8: Make pdp allocation more dynamic

From: Daniel Vetter <daniel@ffwll.ch>
To: Michel Thierry <michel.thierry@intel.com>
Cc: intel-gfx@lists.freedesktop.org, akash.goel@intel.com
Subject: Re: [PATCH v6 02/19] drm/i915/gen8: Make pdp allocation more dynamic
Date: Thu, 6 Aug 2015 14:28:45 +0200	[thread overview]
Message-ID: <20150806122845.GG17734@phenom.ffwll.local> (raw)
In-Reply-To: <55C2307D.9000206@intel.com>

On Wed, Aug 05, 2015 at 04:49:17PM +0100, Michel Thierry wrote:
> On 8/5/2015 4:31 PM, Daniel Vetter wrote:
> >On Wed, Jul 29, 2015 at 05:23:46PM +0100, Michel Thierry wrote:
> >>This transitional patch doesn't do much for the existing code. However,
> >>it should make upcoming patches to use the full 48b address space a bit
> >>easier.
> >
> >commit message should also mention how exactly it's more dynamic and why
> >exactly that's useful ... It's ofc possible to infer that from the
> >context, but that won't be the case any more if you look at the patch
> >alone (with git blame or after a bisect). Please follow up with a few
> >words so I can add them to the commit message.
> >-Daniel
> >
> 
> Hi Daniel,
> Agree the description is vague. Here's the updated commit message, let me
> know what you think (and if you want a new patch):
> 
> drm/i915/gen8: Make pdp allocation more dynamic
> 
> This transitional patch doesn't do much for the existing code. However,
> it should make upcoming patches to use the full 48b address space a bit
> easier.
> 
> 32-bit ppgtt uses just 4 PDPs, while 48-bit ppgtt will have up-to 512;
> this patch prepares the existing functions to query the right number of pdps
> at run-time. This also means that used_pdpes should also be allocated during
> ppgtt_init, as the bitmap size will depend on the ppgtt address range
> selected.

Existing patch amended, thanks.
-Daniel

> 
> v2: Renamed  pdp_free to be similar to  pd/pt (unmap_and_free_pdp).
> v3: To facilitate testing, 48b mode will be available on Broadwell and
> GEN9+, when i915.enable_ppgtt = 3.
> v4: Rebase after s/page_tables/page_table/, added extra information
> about 4-level page table formats and use IS_ENABLED macro.
> v5: Check CONFIG_X86_64 instead of CONFIG_64BIT.
> v6: Rebase after Mika's ppgtt cleanup / scratch merge patch series, and
> follow
> his nomenclature in pdp functions (there is no alloc_pdp yet).
> v7: Rebase after merged version of Mika's ppgtt cleanup patch series.
> v8: Rebase after final merged version of Mika's ppgtt/scratch patches.
> v9: Introduce PML4 (and 48-bit checks) until next patch (Akash).
> v10: Also use test_bit to detect when pd/pt are already allocated (Akash)
> v11:
> 
> Cc: Akash Goel <akash.goel@intel.com>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com> (v2+)

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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