Re: [PATCH v6 06/19] drm/i915/gen8: Add PML4 structure

From: Michel Thierry <michel.thierry@intel.com>
To: "Goel, Akash" <akash.goel@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v6 06/19] drm/i915/gen8: Add PML4 structure
Date: Thu, 30 Jul 2015 10:31:51 +0100	[thread overview]
Message-ID: <55B9EF07.6060409@intel.com> (raw)
In-Reply-To: <55B9A182.4080807@intel.com>

On 7/30/2015 5:01 AM, Goel, Akash wrote:
> On 7/29/2015 9:53 PM, Michel Thierry wrote:
>> Introduces the Page Map Level 4 (PML4), ie. the new top level structure
>> of the page tables.
>>
>> To facilitate testing, 48b mode will be available on Broadwell and
>> GEN9+, when i915.enable_ppgtt = 3.
>>
>> v2: Remove unnecessary CONFIG_X86_64 checks, ppgtt code is already
>> 32/64-bit safe (Chris).
>> v3: Add goto free_scratch in temp 48-bit mode init code (Akash).
>>
>> Cc: Akash Goel <akash.goel@intel.com>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> @@ -557,6 +563,8 @@ static void free_pdp(struct drm_device *dev,
>>                struct i915_page_directory_pointer *pdp)
>>   {
>>       __pdp_fini(pdp);
>> +    if (USES_FULL_48BIT_PPGTT(dev))
>> +        kfree(pdp);
>
> Sorry for the late comment.
> This change is a bit of distraction here, should be moved to the
> following 'alloc/free for 4lvl' patch.
>
> Best regards
> Akash
>

kfree(pdp) moved to patch 7/19.
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