Re: [PATCH 2/4] drm/i915: Use adjusted mode clk for calculating DSI clk

From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Gaurav K Singh <gaurav.k.singh@intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>, rakshmi.bhatia@intel.com
Subject: Re: [PATCH 2/4] drm/i915: Use adjusted mode clk for calculating DSI clk
Date: Wed, 16 Sep 2015 16:10:38 +0300	[thread overview]
Message-ID: <20150916131038.GH26517@intel.com> (raw)
In-Reply-To: <1442395121-19251-3-git-send-email-gaurav.k.singh@intel.com>

On Wed, Sep 16, 2015 at 02:48:39PM +0530, Gaurav K Singh wrote:
> Earlier, pclk was getting used for calculating DSI clk. For single link
> MIPI panels, it will work fine. But for dual link MIPI, since pclk gets
> halved, DSI clk will have a wrong value.

Shouldn't we then do pclk*!!dual_link. pclk can be higher than the
dotclock due to the pixel overlap / burst mode stuff, no?

> 
> Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index bf0f622..a53ccc9 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -468,12 +468,14 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port)
>  static bool bxt_configure_dsi_pll(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> +	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> +	struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	u8 dsi_ratio;
>  	u32 dsi_clk;
>  	u32 val;
>  
> -	dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format,
> +	dsi_clk = dsi_clk_from_pclk(mode->clock, intel_dsi->pixel_format,
>  			intel_dsi->lane_count);
>  
>  	/*
> -- 
> 1.7.9.5
> 
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-- 
Ville Syrjälä
Intel OTC
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