From: Marc Zyngier <marc.zyngier@arm.com>
To: Pavel Fedin <p.fedin@samsung.com>
Cc: 'Andre Przywara' <andre.przywara@arm.com>,
<christoffer.dall@linaro.org>, <eric.auger@linaro.org>,
<kvmarm@lists.cs.columbia.edu>,
<linux-arm-kernel@lists.infradead.org>, <kvm@vger.kernel.org>
Subject: Re: [PATCH v3 00/16] KVM: arm64: GICv3 ITS emulation
Date: Wed, 7 Oct 2015 20:48:10 +0100 [thread overview]
Message-ID: <20151007204810.66e2b1d6@arm.com> (raw)
In-Reply-To: <02c301d1012b$42cb8270$c8628750$@samsung.com>
On Wed, 7 Oct 2015 21:09:07 +0300
Pavel Fedin <p.fedin@samsung.com> wrote:
> Hello!
>
> > LPIs do not have an active state, at the redistributor or otherwise.
>
> Then what do they become after they were ACK'ed and before EOI'ed?
Nothing. They are gone. What is left at the CPU interface is the active
priority.
> I tried to google up this thing, and came up with this email:
> http://www.spinics.net/lists/kvm-arm/msg16032.html. It says that "SW must issue a write to EOI to
> clear the active priorities register, hence the CPU interface still requires an active state for
> LPIs". They give a link to some document which seems to be top-secret and never published, because
> my arch reference manual does not have section 4.8.3 named "Properties of LPI".
Your architecture document has a section 1.2.1 which contains the
sentence: "LPIs do not have an active state, and therefore do not
require explicit deactivation.". It also has 1.2.2 ("Interrupt states")
that repeatedly states the same thing. Finally, the email you quote is
about priority drop vs deactivation, not about the active state of an
LPI.
> And another thread,
> http://lists.xen.org/archives/html/xen-devel/2014-09/msg01141.html,
> says that virtual LPIs actually do have active state in LR.
Or not. Read again. The only case where something vaguely relevant
happens is when you inject a virtual SPI backed by a HW LPI. In that
case, the LR does have an active state (of course, this is an SPI). Or
when you inject a virtual LPI backed by a HW SPI (in which case the
relevant active state is in the physical distributor, not in the LR).
I'd appreciate if you could try to read and understand the architecture
spec instead of randomly googling and quoting various bits of
irrelevant information.
If something is unclear in the architecture specification (yes, this
is complicated and sometimes confusing), please ask relevant questions.
At the moment, you're just asserting fallacies, and I'd rather spend
time doing something useful instead of setting the record straight
again and again.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <marc.zyngier@arm.com>
To: Pavel Fedin <p.fedin@samsung.com>
Cc: 'Andre Przywara' <andre.przywara@arm.com>,
christoffer.dall@linaro.org, eric.auger@linaro.org,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org
Subject: Re: [PATCH v3 00/16] KVM: arm64: GICv3 ITS emulation
Date: Wed, 7 Oct 2015 20:48:10 +0100 [thread overview]
Message-ID: <20151007204810.66e2b1d6@arm.com> (raw)
In-Reply-To: <02c301d1012b$42cb8270$c8628750$@samsung.com>
On Wed, 7 Oct 2015 21:09:07 +0300
Pavel Fedin <p.fedin@samsung.com> wrote:
> Hello!
>
> > LPIs do not have an active state, at the redistributor or otherwise.
>
> Then what do they become after they were ACK'ed and before EOI'ed?
Nothing. They are gone. What is left at the CPU interface is the active
priority.
> I tried to google up this thing, and came up with this email:
> http://www.spinics.net/lists/kvm-arm/msg16032.html. It says that "SW must issue a write to EOI to
> clear the active priorities register, hence the CPU interface still requires an active state for
> LPIs". They give a link to some document which seems to be top-secret and never published, because
> my arch reference manual does not have section 4.8.3 named "Properties of LPI".
Your architecture document has a section 1.2.1 which contains the
sentence: "LPIs do not have an active state, and therefore do not
require explicit deactivation.". It also has 1.2.2 ("Interrupt states")
that repeatedly states the same thing. Finally, the email you quote is
about priority drop vs deactivation, not about the active state of an
LPI.
> And another thread,
> http://lists.xen.org/archives/html/xen-devel/2014-09/msg01141.html,
> says that virtual LPIs actually do have active state in LR.
Or not. Read again. The only case where something vaguely relevant
happens is when you inject a virtual SPI backed by a HW LPI. In that
case, the LR does have an active state (of course, this is an SPI). Or
when you inject a virtual LPI backed by a HW SPI (in which case the
relevant active state is in the physical distributor, not in the LR).
I'd appreciate if you could try to read and understand the architecture
spec instead of randomly googling and quoting various bits of
irrelevant information.
If something is unclear in the architecture specification (yes, this
is complicated and sometimes confusing), please ask relevant questions.
At the moment, you're just asserting fallacies, and I'd rather spend
time doing something useful instead of setting the record straight
again and again.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
WARNING: multiple messages have this Message-ID (diff)
From: marc.zyngier@arm.com (Marc Zyngier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 00/16] KVM: arm64: GICv3 ITS emulation
Date: Wed, 7 Oct 2015 20:48:10 +0100 [thread overview]
Message-ID: <20151007204810.66e2b1d6@arm.com> (raw)
In-Reply-To: <02c301d1012b$42cb8270$c8628750$@samsung.com>
On Wed, 7 Oct 2015 21:09:07 +0300
Pavel Fedin <p.fedin@samsung.com> wrote:
> Hello!
>
> > LPIs do not have an active state, at the redistributor or otherwise.
>
> Then what do they become after they were ACK'ed and before EOI'ed?
Nothing. They are gone. What is left at the CPU interface is the active
priority.
> I tried to google up this thing, and came up with this email:
> http://www.spinics.net/lists/kvm-arm/msg16032.html. It says that "SW must issue a write to EOI to
> clear the active priorities register, hence the CPU interface still requires an active state for
> LPIs". They give a link to some document which seems to be top-secret and never published, because
> my arch reference manual does not have section 4.8.3 named "Properties of LPI".
Your architecture document has a section 1.2.1 which contains the
sentence: "LPIs do not have an active state, and therefore do not
require explicit deactivation.". It also has 1.2.2 ("Interrupt states")
that repeatedly states the same thing. Finally, the email you quote is
about priority drop vs deactivation, not about the active state of an
LPI.
> And another thread,
> http://lists.xen.org/archives/html/xen-devel/2014-09/msg01141.html,
> says that virtual LPIs actually do have active state in LR.
Or not. Read again. The only case where something vaguely relevant
happens is when you inject a virtual SPI backed by a HW LPI. In that
case, the LR does have an active state (of course, this is an SPI). Or
when you inject a virtual LPI backed by a HW SPI (in which case the
relevant active state is in the physical distributor, not in the LR).
I'd appreciate if you could try to read and understand the architecture
spec instead of randomly googling and quoting various bits of
irrelevant information.
If something is unclear in the architecture specification (yes, this
is complicated and sometimes confusing), please ask relevant questions.
At the moment, you're just asserting fallacies, and I'd rather spend
time doing something useful instead of setting the record straight
again and again.
Thanks,
M.
--
Jazz is not dead. It just smells funny.
next prev parent reply other threads:[~2015-10-07 19:48 UTC|newest]
Thread overview: 101+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-07 14:55 [PATCH v3 00/16] KVM: arm64: GICv3 ITS emulation Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 01/16] KVM: arm/arm64: VGIC: don't track used LRs in the distributor Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 02/16] KVM: arm/arm64: remove now unused code after stay-in-LR rework Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 03/16] KVM: extend struct kvm_msi to hold a 32-bit device ID Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 04/16] KVM: arm/arm64: add emulation model specific destroy function Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 05/16] KVM: arm/arm64: extend arch CAP checks to allow per-VM capabilities Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 06/16] KVM: arm/arm64: make GIC frame address initialization model specific Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 07/16] KVM: arm64: Introduce new MMIO region for the ITS base address Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 08/16] KVM: arm64: handle ITS related GICv3 redistributor registers Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-22 15:46 ` Pavel Fedin
2015-10-22 15:46 ` Pavel Fedin
2015-10-22 15:55 ` Pavel Fedin
2015-10-22 15:55 ` Pavel Fedin
2015-10-07 14:55 ` [PATCH v3 09/16] KVM: arm64: introduce ITS emulation file with stub functions Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 10/16] KVM: arm64: implement basic ITS register handlers Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 11/16] KVM: arm64: add data structures to model ITS interrupt translation Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 12/16] KVM: arm64: handle pending bit for LPIs in ITS emulation Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 15:10 ` Pavel Fedin
2015-10-07 15:10 ` Pavel Fedin
2015-10-07 15:35 ` Marc Zyngier
2015-10-07 15:35 ` Marc Zyngier
2015-10-07 15:46 ` Pavel Fedin
2015-10-07 15:46 ` Pavel Fedin
2015-10-07 15:49 ` Marc Zyngier
2015-10-07 15:49 ` Marc Zyngier
2015-10-12 7:40 ` Pavel Fedin
2015-10-12 7:40 ` Pavel Fedin
2015-10-12 11:39 ` Pavel Fedin
2015-10-12 11:39 ` Pavel Fedin
2015-10-12 14:17 ` Andre Przywara
2015-10-12 14:17 ` Andre Przywara
2015-10-07 14:55 ` [PATCH v3 13/16] KVM: arm64: sync LPI configuration and pending tables Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-21 11:29 ` Pavel Fedin
2015-10-21 11:29 ` Pavel Fedin
2015-10-07 14:55 ` [PATCH v3 14/16] KVM: arm64: implement ITS command queue command handlers Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-14 12:26 ` Pavel Fedin
2015-10-14 12:26 ` Pavel Fedin
2015-10-07 14:55 ` [PATCH v3 15/16] KVM: arm64: implement MSI injection in ITS emulation Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-11-25 13:28 ` Pavel Fedin
2015-11-25 13:28 ` Pavel Fedin
2015-10-07 14:55 ` [PATCH v3 16/16] KVM: arm64: enable ITS emulation as a virtual MSI controller Andre Przywara
2015-10-07 14:55 ` Andre Przywara
2015-10-07 16:05 ` [PATCH v3 00/16] KVM: arm64: GICv3 ITS emulation Pavel Fedin
2015-10-07 16:05 ` Pavel Fedin
2015-10-07 16:22 ` Marc Zyngier
2015-10-07 16:22 ` Marc Zyngier
2015-10-07 18:09 ` Pavel Fedin
2015-10-07 18:09 ` Pavel Fedin
2015-10-07 19:48 ` Marc Zyngier [this message]
2015-10-07 19:48 ` Marc Zyngier
2015-10-07 19:48 ` Marc Zyngier
2015-10-08 8:41 ` Pavel Fedin
2015-10-08 8:41 ` Pavel Fedin
2015-10-10 15:37 ` Christoffer Dall
2015-10-10 15:37 ` Christoffer Dall
2015-10-12 14:12 ` Andre Przywara
2015-10-12 14:12 ` Andre Przywara
2015-10-12 15:18 ` Pavel Fedin
2015-10-12 15:18 ` Pavel Fedin
2015-10-14 8:48 ` Eric Auger
2015-10-14 8:48 ` Eric Auger
2015-10-14 8:50 ` Pavel Fedin
2015-10-14 8:50 ` Pavel Fedin
2015-10-13 15:46 ` Pavel Fedin
2015-10-13 15:46 ` Pavel Fedin
2016-03-09 11:35 ` Tomasz Nowicki
2016-03-09 11:35 ` Tomasz Nowicki
2016-03-13 18:16 ` Christoffer Dall
2016-03-13 18:16 ` Christoffer Dall
2016-03-14 11:13 ` Andre Przywara
2016-03-14 11:13 ` Andre Przywara
2016-03-14 17:29 ` Peter Maydell
2016-03-14 17:29 ` Peter Maydell
2016-03-14 17:54 ` Marc Zyngier
2016-03-14 17:54 ` Marc Zyngier
2016-03-14 18:20 ` Andre Przywara
2016-03-14 18:20 ` Andre Przywara
2016-03-14 18:36 ` Marc Zyngier
2016-03-14 18:36 ` Marc Zyngier
2016-03-18 9:40 ` Christoffer Dall
2016-03-18 9:40 ` Christoffer Dall
2016-03-18 17:14 ` Peter Maydell
2016-03-18 17:14 ` Peter Maydell
2016-03-18 9:38 ` Christoffer Dall
2016-03-18 9:38 ` Christoffer Dall
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