From: Rob Herring <robh@kernel.org>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>,
Florian Fainelli <f.fainelli@gmail.com>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
LABBE Corentin <clabbe.montjoie@gmail.com>
Subject: Re: [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY
Date: Thu, 7 Apr 2016 12:57:25 -0500 [thread overview]
Message-ID: <20160407175725.GG32257@rob-hp-laptop> (raw)
In-Reply-To: <1459786954-12649-2-git-send-email-wens@csie.org>
On Tue, Apr 05, 2016 at 12:22:30AM +0800, Chen-Yu Tsai wrote:
> The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
> configured through a memory mapped hardware register.
>
> This same register also configures the MAC interface mode and TX clock
> source. Also covered by the register, but not supported in these bindings,
> are TX/RX clock delay chains and inverters, and an RMII module.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt
Acked-by: Rob Herring <robh@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org>
To: Chen-Yu Tsai <wens@csie.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org,
Florian Fainelli <f.fainelli@gmail.com>,
Pawel Moll <pawel.moll@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
LABBE Corentin <clabbe.montjoie@gmail.com>,
Kumar Gala <galak@codeaurora.org>,
Maxime Ripard <maxime.ripard@free-electrons.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY
Date: Thu, 7 Apr 2016 12:57:25 -0500 [thread overview]
Message-ID: <20160407175725.GG32257@rob-hp-laptop> (raw)
In-Reply-To: <1459786954-12649-2-git-send-email-wens@csie.org>
On Tue, Apr 05, 2016 at 12:22:30AM +0800, Chen-Yu Tsai wrote:
> The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
> configured through a memory mapped hardware register.
>
> This same register also configures the MAC interface mode and TX clock
> source. Also covered by the register, but not supported in these bindings,
> are TX/RX clock delay chains and inverters, and an RMII module.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt
Acked-by: Rob Herring <robh@kernel.org>
WARNING: multiple messages have this Message-ID (diff)
From: robh@kernel.org (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY
Date: Thu, 7 Apr 2016 12:57:25 -0500 [thread overview]
Message-ID: <20160407175725.GG32257@rob-hp-laptop> (raw)
In-Reply-To: <1459786954-12649-2-git-send-email-wens@csie.org>
On Tue, Apr 05, 2016 at 12:22:30AM +0800, Chen-Yu Tsai wrote:
> The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
> configured through a memory mapped hardware register.
>
> This same register also configures the MAC interface mode and TX clock
> source. Also covered by the register, but not supported in these bindings,
> are TX/RX clock delay chains and inverters, and an RMII module.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> .../bindings/net/allwinner,sun8i-h3-ephy.txt | 44 ++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/allwinner,sun8i-h3-ephy.txt
Acked-by: Rob Herring <robh@kernel.org>
next prev parent reply other threads:[~2016-04-07 18:03 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-04 16:22 [PATCH RFC 0/5] net: phy: sun8i-h3-ephy: Add Allwinner H3 Ethernet PHY driver Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-04 16:22 ` [PATCH RFC 1/5] net: phy: sun8i-h3-ephy: Add bindings for Allwinner H3 Ethernet PHY Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-07 17:57 ` Rob Herring [this message]
2016-04-07 17:57 ` Rob Herring
2016-04-07 17:57 ` Rob Herring
2016-04-11 19:23 ` Florian Fainelli
2016-04-11 19:23 ` Florian Fainelli
2016-04-12 1:38 ` Chen-Yu Tsai
2016-04-12 1:38 ` Chen-Yu Tsai
2016-05-07 5:30 ` Chen-Yu Tsai
2016-05-07 5:30 ` Chen-Yu Tsai
2016-05-07 5:30 ` Chen-Yu Tsai
2016-05-07 8:14 ` Hans de Goede
2016-05-07 8:14 ` Hans de Goede
2016-04-04 16:22 ` [PATCH RFC 2/5] net: phy: sun8i-h3-ephy: Add driver " Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-11 19:23 ` Florian Fainelli
2016-04-11 19:23 ` Florian Fainelli
2016-04-11 19:23 ` Florian Fainelli
2016-04-14 2:04 ` Chen-Yu Tsai
2016-04-14 2:04 ` Chen-Yu Tsai
2016-04-04 16:22 ` [PATCH RFC 3/5] ARM: dts: sun8i-h3: Add H3 Ethernet PHY device node to sun8i-h3.dtsi Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-04 16:22 ` [PATCH RFC 4/5] ARM: dts: sun8i-h3: Add Ethernet controller " Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-04 16:22 ` [PATCH RFC 5/5] ARM: dts: sun8i: Enable Ethernet controller on the Orange PI PC Chen-Yu Tsai
2016-04-04 16:22 ` Chen-Yu Tsai
2016-04-11 19:25 ` Florian Fainelli
2016-04-11 19:25 ` Florian Fainelli
2016-04-11 19:25 ` Florian Fainelli
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