From: catalin.marinas@arm.com (Catalin Marinas)
To: linux-arm-kernel@lists.infradead.org
Subject: [kernel-hardening] [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
Date: Mon, 15 Aug 2016 10:48:42 +0100 [thread overview]
Message-ID: <20160815094842.GB22320@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <CAKv+Gu9hz_=GSRYgW3RueVhUA8F3HaM5DC_8Jkbx1JHF3x5mKg@mail.gmail.com>
On Sat, Aug 13, 2016 at 11:13:58AM +0200, Ard Biesheuvel wrote:
> On 12 August 2016 at 17:27, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > This is the first (public) attempt at emulating PAN by disabling
> > TTBR0_EL1 accesses on arm64.
>
> I take it using TCR_EL1.EPD0 is too expensive?
It would require full TLB invalidation on entering/exiting the kernel
and again for any user access. That's because the architecture allows
this bit to be cached in the TLB so without TLBI we wouldn't have any
guarantee that the actual PAN was toggled. I'm not sure it's even clear
whether a TLBI by ASID or a local one would suffice (likely OK for the
latter).
While I don't have numbers currently, it would be hard to test on the
multitude of partner ARMv8 implementations, especially since that's not
something people would expect to optimise the hardware for.
--
Catalin
WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: kernel-hardening@lists.openwall.com,
James Morse <james.morse@arm.com>,
Julien Grall <julien.grall@arm.com>,
Will Deacon <will.deacon@arm.com>,
Kees Cook <keescook@chromium.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [kernel-hardening] [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching
Date: Mon, 15 Aug 2016 10:48:42 +0100 [thread overview]
Message-ID: <20160815094842.GB22320@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <CAKv+Gu9hz_=GSRYgW3RueVhUA8F3HaM5DC_8Jkbx1JHF3x5mKg@mail.gmail.com>
On Sat, Aug 13, 2016 at 11:13:58AM +0200, Ard Biesheuvel wrote:
> On 12 August 2016 at 17:27, Catalin Marinas <catalin.marinas@arm.com> wrote:
> > This is the first (public) attempt at emulating PAN by disabling
> > TTBR0_EL1 accesses on arm64.
>
> I take it using TCR_EL1.EPD0 is too expensive?
It would require full TLB invalidation on entering/exiting the kernel
and again for any user access. That's because the architecture allows
this bit to be cached in the TLB so without TLBI we wouldn't have any
guarantee that the actual PAN was toggled. I'm not sure it's even clear
whether a TLBI by ASID or a local one would suffice (likely OK for the
latter).
While I don't have numbers currently, it would be hard to test on the
multitude of partner ARMv8 implementations, especially since that's not
something people would expect to optimise the hardware for.
--
Catalin
next prev parent reply other threads:[~2016-08-15 9:48 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-12 15:27 [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] " Catalin Marinas
2016-08-12 15:27 ` [PATCH 1/7] arm64: Factor out PAN enabling/disabling into separate uaccess_* macros Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] " Catalin Marinas
2016-08-12 15:27 ` [PATCH 2/7] arm64: Factor out TTBR0_EL1 setting into a specific asm macro Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] " Catalin Marinas
2016-08-12 15:27 ` [PATCH 3/7] arm64: Introduce uaccess_{disable, enable} functionality based on TTBR0_EL1 Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] [PATCH 3/7] arm64: Introduce uaccess_{disable,enable} " Catalin Marinas
2016-08-12 15:27 ` [PATCH 4/7] arm64: Disable TTBR0_EL1 during normal kernel execution Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] " Catalin Marinas
2016-08-15 11:18 ` Mark Rutland
2016-08-15 11:18 ` [kernel-hardening] " Mark Rutland
2016-08-15 16:39 ` Catalin Marinas
2016-08-15 16:39 ` [kernel-hardening] " Catalin Marinas
2016-08-12 15:27 ` [PATCH 5/7] arm64: Handle faults caused by inadvertent user access with PAN enabled Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] " Catalin Marinas
2016-08-12 15:27 ` [PATCH 6/7] arm64: xen: Enable user access before a privcmd hvc call Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] " Catalin Marinas
2016-08-15 9:58 ` Julien Grall
2016-08-15 9:58 ` [kernel-hardening] " Julien Grall
2016-08-15 18:00 ` Stefano Stabellini
2016-08-15 18:00 ` [kernel-hardening] " Stefano Stabellini
2016-08-15 18:00 ` Stefano Stabellini
2016-08-15 9:58 ` Julien Grall
2016-08-12 15:27 ` [PATCH 7/7] arm64: Enable CONFIG_ARM64_TTBR0_PAN Catalin Marinas
2016-08-12 15:27 ` [kernel-hardening] " Catalin Marinas
2016-08-12 18:04 ` [PATCH 0/7] arm64: Privileged Access Never using TTBR0_EL1 switching Kees Cook
2016-08-12 18:04 ` [kernel-hardening] " Kees Cook
2016-08-12 18:22 ` Catalin Marinas
2016-08-12 18:22 ` [kernel-hardening] " Catalin Marinas
2016-08-13 9:13 ` [kernel-hardening] " Ard Biesheuvel
2016-08-13 9:13 ` Ard Biesheuvel
2016-08-15 9:48 ` Catalin Marinas [this message]
2016-08-15 9:48 ` Catalin Marinas
2016-08-15 9:58 ` Mark Rutland
2016-08-15 9:58 ` Mark Rutland
2016-08-15 10:02 ` Ard Biesheuvel
2016-08-15 10:02 ` Ard Biesheuvel
2016-08-15 10:06 ` Mark Rutland
2016-08-15 10:06 ` Mark Rutland
2016-08-15 10:10 ` Will Deacon
2016-08-15 10:10 ` Will Deacon
2016-08-15 10:15 ` Mark Rutland
2016-08-15 10:15 ` Mark Rutland
2016-08-15 10:21 ` Will Deacon
2016-08-15 10:21 ` Will Deacon
2016-08-15 10:21 ` Ard Biesheuvel
2016-08-15 10:21 ` Ard Biesheuvel
2016-08-15 10:30 ` Will Deacon
2016-08-15 10:30 ` Will Deacon
2016-08-15 10:31 ` Ard Biesheuvel
2016-08-15 10:31 ` Ard Biesheuvel
2016-08-15 10:37 ` Will Deacon
2016-08-15 10:37 ` Will Deacon
2016-08-15 10:43 ` Ard Biesheuvel
2016-08-15 10:43 ` Ard Biesheuvel
2016-08-15 10:52 ` Catalin Marinas
2016-08-15 10:52 ` Catalin Marinas
2016-08-15 10:56 ` Ard Biesheuvel
2016-08-15 10:56 ` Ard Biesheuvel
2016-08-15 11:02 ` Will Deacon
2016-08-15 11:02 ` Will Deacon
2016-08-15 16:13 ` Catalin Marinas
2016-08-15 16:13 ` Catalin Marinas
2016-08-15 19:04 ` Ard Biesheuvel
2016-08-15 19:04 ` Ard Biesheuvel
2016-08-15 11:00 ` Will Deacon
2016-08-15 11:00 ` Will Deacon
2016-08-15 10:30 ` Mark Rutland
2016-08-15 10:30 ` Mark Rutland
2016-08-15 10:08 ` Will Deacon
2016-08-15 10:08 ` Will Deacon
2016-08-26 15:39 ` David Brown
2016-08-26 15:39 ` David Brown
2016-08-26 17:24 ` Catalin Marinas
2016-08-26 17:24 ` Catalin Marinas
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