From: Sean Paul <seanpaul@chromium.org>
To: John Keeping <john@metanate.com>
Cc: Mark Yao <mark.yao@rock-chips.com>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
Chris Zhong <zyw@rock-chips.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration
Date: Tue, 31 Jan 2017 14:03:52 -0500 [thread overview]
Message-ID: <20170131190352.GB20076@art_vandelay> (raw)
In-Reply-To: <20170129132444.25251-18-john@metanate.com>
On Sun, Jan 29, 2017 at 01:24:37PM +0000, John Keeping wrote:
> The multiplication ratio for the PLL is required to be even due to the
> use of a "by 2 pre-scaler". Currently we are likely to end up with an
> odd multiplier even though there is an equivalent set of parameters with
> an even multiplier.
>
> For example, using the 324MHz bit rate with a reference clock of 24MHz
> we end up with M = 27, N = 2 whereas the example in the PHY databook
> gives M = 54, N = 4 for this bit rate and reference clock.
>
> By walking down through the available multiplier instead of up we are
> more likely to hit an even multiplier. With the above example we do now
> get M = 54, N = 4 as given by the databook.
>
> While doing this, change the loop limits to encode the actual limits on
> the divisor, which are:
>
> 40MHz >= (pllref / N) >= 5MHz
>
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v3
> Unchanged in v2
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 85edf6dd2bac..dcb66a21e1f1 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
> pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
> tmp = pllref;
>
> - for (i = 1; i < 6; i++) {
> + for (i = pllref / 5; i > (pllref / 40); i--) {
I've convinced myself that this is right, but it took reading through the commit
message a few times. I think this code would benefit greatly from a comment so
readers don't need to go through git history.
With that,
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> pre = pllref / i;
> if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
> tmp = target_mbps % pre;
> --
> 2.11.0.197.gb556de5.dirty
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
WARNING: multiple messages have this Message-ID (diff)
From: Sean Paul <seanpaul@chromium.org>
To: John Keeping <john@metanate.com>
Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
Chris Zhong <zyw@rock-chips.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration
Date: Tue, 31 Jan 2017 14:03:52 -0500 [thread overview]
Message-ID: <20170131190352.GB20076@art_vandelay> (raw)
In-Reply-To: <20170129132444.25251-18-john@metanate.com>
On Sun, Jan 29, 2017 at 01:24:37PM +0000, John Keeping wrote:
> The multiplication ratio for the PLL is required to be even due to the
> use of a "by 2 pre-scaler". Currently we are likely to end up with an
> odd multiplier even though there is an equivalent set of parameters with
> an even multiplier.
>
> For example, using the 324MHz bit rate with a reference clock of 24MHz
> we end up with M = 27, N = 2 whereas the example in the PHY databook
> gives M = 54, N = 4 for this bit rate and reference clock.
>
> By walking down through the available multiplier instead of up we are
> more likely to hit an even multiplier. With the above example we do now
> get M = 54, N = 4 as given by the databook.
>
> While doing this, change the loop limits to encode the actual limits on
> the divisor, which are:
>
> 40MHz >= (pllref / N) >= 5MHz
>
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v3
> Unchanged in v2
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 85edf6dd2bac..dcb66a21e1f1 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
> pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
> tmp = pllref;
>
> - for (i = 1; i < 6; i++) {
> + for (i = pllref / 5; i > (pllref / 40); i--) {
I've convinced myself that this is right, but it took reading through the commit
message a few times. I think this code would benefit greatly from a comment so
readers don't need to go through git history.
With that,
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> pre = pllref / i;
> if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
> tmp = target_mbps % pre;
> --
> 2.11.0.197.gb556de5.dirty
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
WARNING: multiple messages have this Message-ID (diff)
From: seanpaul@chromium.org (Sean Paul)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration
Date: Tue, 31 Jan 2017 14:03:52 -0500 [thread overview]
Message-ID: <20170131190352.GB20076@art_vandelay> (raw)
In-Reply-To: <20170129132444.25251-18-john@metanate.com>
On Sun, Jan 29, 2017 at 01:24:37PM +0000, John Keeping wrote:
> The multiplication ratio for the PLL is required to be even due to the
> use of a "by 2 pre-scaler". Currently we are likely to end up with an
> odd multiplier even though there is an equivalent set of parameters with
> an even multiplier.
>
> For example, using the 324MHz bit rate with a reference clock of 24MHz
> we end up with M = 27, N = 2 whereas the example in the PHY databook
> gives M = 54, N = 4 for this bit rate and reference clock.
>
> By walking down through the available multiplier instead of up we are
> more likely to hit an even multiplier. With the above example we do now
> get M = 54, N = 4 as given by the databook.
>
> While doing this, change the loop limits to encode the actual limits on
> the divisor, which are:
>
> 40MHz >= (pllref / N) >= 5MHz
>
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> Unchanged in v3
> Unchanged in v2
>
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index 85edf6dd2bac..dcb66a21e1f1 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -522,7 +522,7 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi,
> pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC);
> tmp = pllref;
>
> - for (i = 1; i < 6; i++) {
> + for (i = pllref / 5; i > (pllref / 40); i--) {
I've convinced myself that this is right, but it took reading through the commit
message a few times. I think this code would benefit greatly from a comment so
readers don't need to go through git history.
With that,
Reviewed-by: Sean Paul <seanpaul@chromium.org>
> pre = pllref / i;
> if ((tmp > (target_mbps % pre)) && (target_mbps / pre < 512)) {
> tmp = target_mbps % pre;
> --
> 2.11.0.197.gb556de5.dirty
>
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Sean Paul, Software Engineer, Google / Chromium OS
next prev parent reply other threads:[~2017-01-31 19:10 UTC|newest]
Thread overview: 209+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-29 13:24 [PATCH v3 00/24] drm/rockchip: MIPI fixes & improvements John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` [PATCH v3 01/24] drm/rockchip: dw-mipi-dsi: don't configure hardware in mode_set for MIPI John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 15:35 ` Sean Paul
2017-01-30 15:35 ` Sean Paul
2017-01-30 15:35 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 02/24] drm/rockchip: dw-mipi-dsi: pass mode in where needed John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 15:40 ` Sean Paul
2017-01-30 15:40 ` Sean Paul
2017-01-30 15:40 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 03/24] drm/rockchip: dw-mipi-dsi: remove mode_set hook John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 15:40 ` Sean Paul
2017-01-30 15:40 ` Sean Paul
2017-01-30 15:40 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 04/24] drm/rockchip: dw-mipi-dsi: fix command header writes John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 15:43 ` Sean Paul
2017-01-30 15:43 ` Sean Paul
2017-01-30 15:43 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 05/24] drm/rockchip: dw-mipi-dsi: fix generic packet status check John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 17:56 ` Sean Paul
2017-01-30 17:56 ` Sean Paul
2017-01-30 17:56 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 06/24] drm/rockchip: dw-mipi-dsi: avoid out-of-bounds read on tx_buf John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 18:01 ` Sean Paul
2017-01-30 18:01 ` Sean Paul
2017-01-30 18:01 ` Sean Paul
2017-01-30 18:16 ` John Keeping
2017-01-30 18:16 ` John Keeping
2017-01-30 18:16 ` John Keeping
2017-01-30 20:09 ` Sean Paul
2017-01-30 20:09 ` Sean Paul
2017-01-30 20:09 ` Sean Paul
2017-01-31 11:45 ` John Keeping
2017-01-31 11:45 ` John Keeping
2017-01-31 11:45 ` John Keeping
2017-01-31 14:48 ` Sean Paul
2017-01-31 14:48 ` Sean Paul
2017-01-31 14:48 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 07/24] drm/rockchip: dw-mipi-dsi: include bad value in error message John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 18:02 ` Sean Paul
2017-01-30 18:02 ` Sean Paul
2017-01-30 18:02 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 08/24] drm/rockchip: dw-mipi-dsi: respect message flags John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 18:19 ` Sean Paul
2017-01-30 18:19 ` Sean Paul
2017-01-30 18:19 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 09/24] drm/rockchip: dw-mipi-dsi: only request HS clock when required John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 18:20 ` Sean Paul
2017-01-30 18:20 ` Sean Paul
2017-01-30 18:20 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 10/24] drm/rockchip: dw-mipi-dsi: don't assume buffer is aligned John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 20:08 ` Sean Paul
2017-01-30 20:08 ` Sean Paul
2017-01-30 20:08 ` Sean Paul
2017-01-31 11:56 ` John Keeping
2017-01-31 11:56 ` John Keeping
2017-01-31 11:56 ` John Keeping
2017-01-31 14:53 ` Sean Paul
2017-01-31 14:53 ` Sean Paul
2017-01-31 14:53 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 11/24] drm/rockchip: dw-mipi-dsi: prepare panel after phy init John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 20:16 ` Sean Paul
2017-01-30 20:16 ` Sean Paul
2017-01-30 20:16 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 12/24] drm/rockchip: dw-mipi-dsi: allow commands in panel_disable John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 20:19 ` Sean Paul
2017-01-30 20:19 ` Sean Paul
2017-01-30 20:19 ` Sean Paul
2017-01-31 12:03 ` John Keeping
2017-01-31 12:03 ` John Keeping
2017-01-31 12:03 ` John Keeping
2017-01-29 13:24 ` [PATCH v3 13/24] drm/rockchip: dw-mipi-dsi: fix escape clock rate John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 20:25 ` Sean Paul
2017-01-30 20:25 ` Sean Paul
2017-01-30 20:25 ` Sean Paul
2017-02-01 17:23 ` John Keeping
2017-02-01 17:23 ` John Keeping
2017-01-29 13:24 ` [PATCH v3 14/24] drm/rockchip: dw-mipi-dsi: ensure PHY is reset John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 20:25 ` Sean Paul
2017-01-30 20:25 ` Sean Paul
2017-01-30 20:25 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 15/24] drm/rockchip: dw-mipi-dsi: configure PHY before enabling John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 20:28 ` Sean Paul
2017-01-30 20:28 ` Sean Paul
2017-01-30 20:28 ` Sean Paul
2017-01-31 12:14 ` John Keeping
2017-01-31 12:14 ` John Keeping
2017-01-31 12:14 ` John Keeping
2017-01-29 13:24 ` [PATCH v3 16/24] drm/rockchip: dw-mipi-dsi: properly configure PHY timing John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 21:57 ` Sean Paul
2017-01-30 21:57 ` Sean Paul
2017-01-30 21:57 ` Sean Paul
2017-01-31 12:39 ` John Keeping
2017-01-31 12:39 ` John Keeping
2017-01-31 12:39 ` John Keeping
2017-01-29 13:24 ` [PATCH v3 17/24] drm/rockchip: dw-mipi-dsi: improve PLL configuration John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-31 19:03 ` Sean Paul [this message]
2017-01-31 19:03 ` Sean Paul
2017-01-31 19:03 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 18/24] drm/rockchip: dw-mipi-dsi: use specific poll helper John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-31 18:45 ` Sean Paul
2017-01-31 18:45 ` Sean Paul
2017-01-31 18:45 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check for N{H,V}SYNC John Keeping
2017-01-29 13:24 ` [PATCH v3 19/24] drm/rockchip: dw-mipi-dsi: use positive check for N{H, V}SYNC John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-31 19:12 ` Sean Paul
2017-01-31 19:12 ` Sean Paul
2017-01-31 19:12 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 20/24] drm/rockchip: vop: test for P{H,V}SYNC John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-31 19:14 ` Sean Paul
2017-01-31 19:14 ` Sean Paul
2017-01-31 19:14 ` Sean Paul
2017-01-29 13:24 ` [PATCH v3 21/24] drm/rockchip: dw-mipi-dsi: defer probe if panel is not loaded John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-31 19:21 ` Sean Paul
2017-01-31 19:21 ` Sean Paul
2017-01-31 19:21 ` Sean Paul
2017-02-10 17:27 ` John Keeping
2017-02-10 17:27 ` John Keeping
2017-02-10 17:27 ` John Keeping
2017-01-29 13:24 ` [PATCH v3 22/24] drm/rockchip: dw-mipi-dsi: support non-burst modes John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-31 19:22 ` Sean Paul
2017-01-31 19:22 ` Sean Paul
2017-01-31 19:22 ` Sean Paul
2017-02-16 3:01 ` Chris Zhong
2017-02-16 3:01 ` Chris Zhong
2017-02-16 3:01 ` Chris Zhong
2017-02-16 14:22 ` John Keeping
2017-02-16 14:22 ` John Keeping
2017-02-16 14:22 ` John Keeping
2017-01-29 13:24 ` [PATCH v3 23/24] drm/rockchip: dw-mipi-dsi: add reset control John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-31 19:28 ` Sean Paul
2017-01-31 19:28 ` Sean Paul
2017-01-31 19:28 ` Sean Paul
2017-02-15 3:38 ` Chris Zhong
2017-02-15 3:38 ` Chris Zhong
2017-02-15 3:38 ` Chris Zhong
2017-02-15 12:39 ` John Keeping
2017-02-15 12:39 ` John Keeping
2017-02-15 12:39 ` John Keeping
2017-02-16 2:12 ` Chris Zhong
2017-02-16 2:12 ` Chris Zhong
2017-02-16 2:12 ` Chris Zhong
2017-02-16 14:11 ` John Keeping
2017-02-16 14:11 ` John Keeping
2017-02-16 14:11 ` John Keeping
2017-01-29 13:24 ` [PATCH v3 24/24] drm/rockchip: dw-mipi-dsi: support read commands John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-29 13:24 ` John Keeping
2017-01-30 15:26 ` Sean Paul
2017-01-30 15:26 ` Sean Paul
2017-01-30 15:26 ` Sean Paul
2017-01-30 18:14 ` John Keeping
2017-01-30 18:14 ` John Keeping
2017-01-30 18:14 ` John Keeping
2017-01-30 20:16 ` Sean Paul
2017-01-30 20:16 ` Sean Paul
2017-01-30 20:16 ` Sean Paul
2017-01-31 12:41 ` John Keeping
2017-01-31 12:41 ` John Keeping
2017-01-31 12:41 ` John Keeping
2017-01-31 14:47 ` Sean Paul
2017-01-31 14:47 ` Sean Paul
2017-01-31 14:47 ` Sean Paul
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