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From: Christoffer Dall <cdall@linaro.org>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
	"Radim Krčmář" <rkrcmar@redhat.com>
Cc: kvm@vger.kernel.org, Marc Zyngier <marc.zyngier@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will.deacon@arm.com>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: [PULL 04/79] arm64: sysreg: subsume GICv3 sysreg definitions
Date: Sun, 23 Apr 2017 19:08:14 +0200	[thread overview]
Message-ID: <20170423170929.27334-5-cdall@linaro.org> (raw)
In-Reply-To: <20170423170929.27334-1-cdall@linaro.org>

From: Mark Rutland <mark.rutland@arm.com>

Unlike most sysreg defintiions, the GICv3 definitions don't have a SYS_
prefix, and they don't live in <asm/sysreg.h>. Additionally, some
definitions are duplicated elsewhere (e.g. in the KVM save/restore
code).

For consistency, and to make it possible to share a common definition
for these sysregs, this patch moves the definitions to <asm/sysreg.h>,
adding a SYS_ prefix, and sorting the registers per their encoding.
Existing users of the definitions are fixed up so that this change is
not problematic.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/include/asm/arch_gicv3.h | 81 ++++++-------------------------------
 arch/arm64/include/asm/sysreg.h     | 52 ++++++++++++++++++++++++
 arch/arm64/kernel/head.S            |  8 ++--
 3 files changed, 69 insertions(+), 72 deletions(-)

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index f37e3a2..1a98bc8 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -20,69 +20,14 @@
 
 #include <asm/sysreg.h>
 
-#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)
-#define ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
-#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)
-#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)
-#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
-#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)
-#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
-#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)
-#define ICC_BPR1_EL1			sys_reg(3, 0, 12, 12, 3)
-
-#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
-
-/*
- * System register definitions
- */
-#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)
-#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
-#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
-#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)
-#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)
-#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)
-#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)
-
-#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)
-#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)
-
-#define ICH_LR0_EL2			__LR0_EL2(0)
-#define ICH_LR1_EL2			__LR0_EL2(1)
-#define ICH_LR2_EL2			__LR0_EL2(2)
-#define ICH_LR3_EL2			__LR0_EL2(3)
-#define ICH_LR4_EL2			__LR0_EL2(4)
-#define ICH_LR5_EL2			__LR0_EL2(5)
-#define ICH_LR6_EL2			__LR0_EL2(6)
-#define ICH_LR7_EL2			__LR0_EL2(7)
-#define ICH_LR8_EL2			__LR8_EL2(0)
-#define ICH_LR9_EL2			__LR8_EL2(1)
-#define ICH_LR10_EL2			__LR8_EL2(2)
-#define ICH_LR11_EL2			__LR8_EL2(3)
-#define ICH_LR12_EL2			__LR8_EL2(4)
-#define ICH_LR13_EL2			__LR8_EL2(5)
-#define ICH_LR14_EL2			__LR8_EL2(6)
-#define ICH_LR15_EL2			__LR8_EL2(7)
-
-#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)
-#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)
-#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)
-#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)
-#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)
-
-#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)
-#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)
-#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)
-#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)
-#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)
-
 #ifndef __ASSEMBLY__
 
 #include <linux/stringify.h>
 #include <asm/barrier.h>
 #include <asm/cacheflush.h>
 
-#define read_gicreg			read_sysreg_s
-#define write_gicreg			write_sysreg_s
+#define read_gicreg(r)			read_sysreg_s(SYS_ ## r)
+#define write_gicreg(v, r)		write_sysreg_s(v, SYS_ ## r)
 
 /*
  * Low-level accessors
@@ -93,13 +38,13 @@
 
 static inline void gic_write_eoir(u32 irq)
 {
-	write_sysreg_s(irq, ICC_EOIR1_EL1);
+	write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
 	isb();
 }
 
 static inline void gic_write_dir(u32 irq)
 {
-	write_sysreg_s(irq, ICC_DIR_EL1);
+	write_sysreg_s(irq, SYS_ICC_DIR_EL1);
 	isb();
 }
 
@@ -107,7 +52,7 @@ static inline u64 gic_read_iar_common(void)
 {
 	u64 irqstat;
 
-	irqstat = read_sysreg_s(ICC_IAR1_EL1);
+	irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
 	dsb(sy);
 	return irqstat;
 }
@@ -124,7 +69,7 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
 	u64 irqstat;
 
 	nops(8);
-	irqstat = read_sysreg_s(ICC_IAR1_EL1);
+	irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
 	nops(4);
 	mb();
 
@@ -133,40 +78,40 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
 
 static inline void gic_write_pmr(u32 val)
 {
-	write_sysreg_s(val, ICC_PMR_EL1);
+	write_sysreg_s(val, SYS_ICC_PMR_EL1);
 }
 
 static inline void gic_write_ctlr(u32 val)
 {
-	write_sysreg_s(val, ICC_CTLR_EL1);
+	write_sysreg_s(val, SYS_ICC_CTLR_EL1);
 	isb();
 }
 
 static inline void gic_write_grpen1(u32 val)
 {
-	write_sysreg_s(val, ICC_GRPEN1_EL1);
+	write_sysreg_s(val, SYS_ICC_GRPEN1_EL1);
 	isb();
 }
 
 static inline void gic_write_sgi1r(u64 val)
 {
-	write_sysreg_s(val, ICC_SGI1R_EL1);
+	write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
 }
 
 static inline u32 gic_read_sre(void)
 {
-	return read_sysreg_s(ICC_SRE_EL1);
+	return read_sysreg_s(SYS_ICC_SRE_EL1);
 }
 
 static inline void gic_write_sre(u32 val)
 {
-	write_sysreg_s(val, ICC_SRE_EL1);
+	write_sysreg_s(val, SYS_ICC_SRE_EL1);
 	isb();
 }
 
 static inline void gic_write_bpr1(u32 val)
 {
-	asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
+	write_sysreg_s(val, SYS_ICC_BPR1_EL1);
 }
 
 #define gic_read_typer(c)		readq_relaxed(c)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 3498d02..9dc30bc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -149,9 +149,20 @@
 #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
 #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
 
+#define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
+
 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
 
+#define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
+#define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
+#define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
+#define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
+#define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
+#define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
+#define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
+#define SYS_ICC_GRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
+
 #define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
 #define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
 
@@ -179,6 +190,47 @@
 
 #define SYS_PMCCFILTR_EL0		sys_reg (3, 3, 14, 15, 7)
 
+#define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
+#define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
+#define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
+#define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
+#define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
+
+#define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
+#define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
+#define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
+#define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
+#define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
+
+#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
+#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
+#define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
+#define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
+#define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
+#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
+#define SYS_ICH_ELSR_EL2		sys_reg(3, 4, 12, 11, 5)
+#define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
+
+#define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
+#define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
+#define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
+#define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
+#define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
+#define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
+#define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
+#define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
+#define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
+
+#define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
+#define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
+#define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
+#define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
+#define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
+#define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
+#define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
+#define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
+#define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
+
 /* Common SCTLR_ELx flags. */
 #define SCTLR_ELx_EE    (1 << 25)
 #define SCTLR_ELx_I	(1 << 12)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 4fb6ccd..95ae40ac 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -594,14 +594,14 @@ set_hcr:
 	cmp	x0, #1
 	b.ne	3f
 
-	mrs_s	x0, ICC_SRE_EL2
+	mrs_s	x0, SYS_ICC_SRE_EL2
 	orr	x0, x0, #ICC_SRE_EL2_SRE	// Set ICC_SRE_EL2.SRE==1
 	orr	x0, x0, #ICC_SRE_EL2_ENABLE	// Set ICC_SRE_EL2.Enable==1
-	msr_s	ICC_SRE_EL2, x0
+	msr_s	SYS_ICC_SRE_EL2, x0
 	isb					// Make sure SRE is now set
-	mrs_s	x0, ICC_SRE_EL2			// Read SRE back,
+	mrs_s	x0, SYS_ICC_SRE_EL2		// Read SRE back,
 	tbz	x0, #0, 3f			// and check that it sticks
-	msr_s	ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults
+	msr_s	SYS_ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults
 
 3:
 #endif
-- 
2.9.0

WARNING: multiple messages have this Message-ID (diff)
From: cdall@linaro.org (Christoffer Dall)
To: linux-arm-kernel@lists.infradead.org
Subject: [PULL 04/79] arm64: sysreg: subsume GICv3 sysreg definitions
Date: Sun, 23 Apr 2017 19:08:14 +0200	[thread overview]
Message-ID: <20170423170929.27334-5-cdall@linaro.org> (raw)
In-Reply-To: <20170423170929.27334-1-cdall@linaro.org>

From: Mark Rutland <mark.rutland@arm.com>

Unlike most sysreg defintiions, the GICv3 definitions don't have a SYS_
prefix, and they don't live in <asm/sysreg.h>. Additionally, some
definitions are duplicated elsewhere (e.g. in the KVM save/restore
code).

For consistency, and to make it possible to share a common definition
for these sysregs, this patch moves the definitions to <asm/sysreg.h>,
adding a SYS_ prefix, and sorting the registers per their encoding.
Existing users of the definitions are fixed up so that this change is
not problematic.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
 arch/arm64/include/asm/arch_gicv3.h | 81 ++++++-------------------------------
 arch/arm64/include/asm/sysreg.h     | 52 ++++++++++++++++++++++++
 arch/arm64/kernel/head.S            |  8 ++--
 3 files changed, 69 insertions(+), 72 deletions(-)

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index f37e3a2..1a98bc8 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -20,69 +20,14 @@
 
 #include <asm/sysreg.h>
 
-#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)
-#define ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
-#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)
-#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)
-#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
-#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)
-#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
-#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)
-#define ICC_BPR1_EL1			sys_reg(3, 0, 12, 12, 3)
-
-#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
-
-/*
- * System register definitions
- */
-#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)
-#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
-#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
-#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)
-#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)
-#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)
-#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)
-
-#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)
-#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)
-
-#define ICH_LR0_EL2			__LR0_EL2(0)
-#define ICH_LR1_EL2			__LR0_EL2(1)
-#define ICH_LR2_EL2			__LR0_EL2(2)
-#define ICH_LR3_EL2			__LR0_EL2(3)
-#define ICH_LR4_EL2			__LR0_EL2(4)
-#define ICH_LR5_EL2			__LR0_EL2(5)
-#define ICH_LR6_EL2			__LR0_EL2(6)
-#define ICH_LR7_EL2			__LR0_EL2(7)
-#define ICH_LR8_EL2			__LR8_EL2(0)
-#define ICH_LR9_EL2			__LR8_EL2(1)
-#define ICH_LR10_EL2			__LR8_EL2(2)
-#define ICH_LR11_EL2			__LR8_EL2(3)
-#define ICH_LR12_EL2			__LR8_EL2(4)
-#define ICH_LR13_EL2			__LR8_EL2(5)
-#define ICH_LR14_EL2			__LR8_EL2(6)
-#define ICH_LR15_EL2			__LR8_EL2(7)
-
-#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)
-#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)
-#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)
-#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)
-#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)
-
-#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)
-#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)
-#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)
-#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)
-#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)
-
 #ifndef __ASSEMBLY__
 
 #include <linux/stringify.h>
 #include <asm/barrier.h>
 #include <asm/cacheflush.h>
 
-#define read_gicreg			read_sysreg_s
-#define write_gicreg			write_sysreg_s
+#define read_gicreg(r)			read_sysreg_s(SYS_ ## r)
+#define write_gicreg(v, r)		write_sysreg_s(v, SYS_ ## r)
 
 /*
  * Low-level accessors
@@ -93,13 +38,13 @@
 
 static inline void gic_write_eoir(u32 irq)
 {
-	write_sysreg_s(irq, ICC_EOIR1_EL1);
+	write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
 	isb();
 }
 
 static inline void gic_write_dir(u32 irq)
 {
-	write_sysreg_s(irq, ICC_DIR_EL1);
+	write_sysreg_s(irq, SYS_ICC_DIR_EL1);
 	isb();
 }
 
@@ -107,7 +52,7 @@ static inline u64 gic_read_iar_common(void)
 {
 	u64 irqstat;
 
-	irqstat = read_sysreg_s(ICC_IAR1_EL1);
+	irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
 	dsb(sy);
 	return irqstat;
 }
@@ -124,7 +69,7 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
 	u64 irqstat;
 
 	nops(8);
-	irqstat = read_sysreg_s(ICC_IAR1_EL1);
+	irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
 	nops(4);
 	mb();
 
@@ -133,40 +78,40 @@ static inline u64 gic_read_iar_cavium_thunderx(void)
 
 static inline void gic_write_pmr(u32 val)
 {
-	write_sysreg_s(val, ICC_PMR_EL1);
+	write_sysreg_s(val, SYS_ICC_PMR_EL1);
 }
 
 static inline void gic_write_ctlr(u32 val)
 {
-	write_sysreg_s(val, ICC_CTLR_EL1);
+	write_sysreg_s(val, SYS_ICC_CTLR_EL1);
 	isb();
 }
 
 static inline void gic_write_grpen1(u32 val)
 {
-	write_sysreg_s(val, ICC_GRPEN1_EL1);
+	write_sysreg_s(val, SYS_ICC_GRPEN1_EL1);
 	isb();
 }
 
 static inline void gic_write_sgi1r(u64 val)
 {
-	write_sysreg_s(val, ICC_SGI1R_EL1);
+	write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
 }
 
 static inline u32 gic_read_sre(void)
 {
-	return read_sysreg_s(ICC_SRE_EL1);
+	return read_sysreg_s(SYS_ICC_SRE_EL1);
 }
 
 static inline void gic_write_sre(u32 val)
 {
-	write_sysreg_s(val, ICC_SRE_EL1);
+	write_sysreg_s(val, SYS_ICC_SRE_EL1);
 	isb();
 }
 
 static inline void gic_write_bpr1(u32 val)
 {
-	asm volatile("msr_s " __stringify(ICC_BPR1_EL1) ", %0" : : "r" (val));
+	write_sysreg_s(val, SYS_ICC_BPR1_EL1);
 }
 
 #define gic_read_typer(c)		readq_relaxed(c)
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 3498d02..9dc30bc 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -149,9 +149,20 @@
 #define SYS_ID_AA64MMFR1_EL1		sys_reg(3, 0, 0, 7, 1)
 #define SYS_ID_AA64MMFR2_EL1		sys_reg(3, 0, 0, 7, 2)
 
+#define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
+
 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
 
+#define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
+#define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
+#define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
+#define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
+#define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
+#define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
+#define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
+#define SYS_ICC_GRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
+
 #define SYS_CTR_EL0			sys_reg(3, 3, 0, 0, 1)
 #define SYS_DCZID_EL0			sys_reg(3, 3, 0, 0, 7)
 
@@ -179,6 +190,47 @@
 
 #define SYS_PMCCFILTR_EL0		sys_reg (3, 3, 14, 15, 7)
 
+#define __SYS__AP0Rx_EL2(x)		sys_reg(3, 4, 12, 8, x)
+#define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
+#define SYS_ICH_AP0R1_EL2		__SYS__AP0Rx_EL2(1)
+#define SYS_ICH_AP0R2_EL2		__SYS__AP0Rx_EL2(2)
+#define SYS_ICH_AP0R3_EL2		__SYS__AP0Rx_EL2(3)
+
+#define __SYS__AP1Rx_EL2(x)		sys_reg(3, 4, 12, 9, x)
+#define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
+#define SYS_ICH_AP1R1_EL2		__SYS__AP1Rx_EL2(1)
+#define SYS_ICH_AP1R2_EL2		__SYS__AP1Rx_EL2(2)
+#define SYS_ICH_AP1R3_EL2		__SYS__AP1Rx_EL2(3)
+
+#define SYS_ICH_VSEIR_EL2		sys_reg(3, 4, 12, 9, 4)
+#define SYS_ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)
+#define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
+#define SYS_ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
+#define SYS_ICH_MISR_EL2		sys_reg(3, 4, 12, 11, 2)
+#define SYS_ICH_EISR_EL2		sys_reg(3, 4, 12, 11, 3)
+#define SYS_ICH_ELSR_EL2		sys_reg(3, 4, 12, 11, 5)
+#define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
+
+#define __SYS__LR0_EL2(x)		sys_reg(3, 4, 12, 12, x)
+#define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
+#define SYS_ICH_LR1_EL2			__SYS__LR0_EL2(1)
+#define SYS_ICH_LR2_EL2			__SYS__LR0_EL2(2)
+#define SYS_ICH_LR3_EL2			__SYS__LR0_EL2(3)
+#define SYS_ICH_LR4_EL2			__SYS__LR0_EL2(4)
+#define SYS_ICH_LR5_EL2			__SYS__LR0_EL2(5)
+#define SYS_ICH_LR6_EL2			__SYS__LR0_EL2(6)
+#define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
+
+#define __SYS__LR8_EL2(x)		sys_reg(3, 4, 12, 13, x)
+#define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
+#define SYS_ICH_LR9_EL2			__SYS__LR8_EL2(1)
+#define SYS_ICH_LR10_EL2		__SYS__LR8_EL2(2)
+#define SYS_ICH_LR11_EL2		__SYS__LR8_EL2(3)
+#define SYS_ICH_LR12_EL2		__SYS__LR8_EL2(4)
+#define SYS_ICH_LR13_EL2		__SYS__LR8_EL2(5)
+#define SYS_ICH_LR14_EL2		__SYS__LR8_EL2(6)
+#define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
+
 /* Common SCTLR_ELx flags. */
 #define SCTLR_ELx_EE    (1 << 25)
 #define SCTLR_ELx_I	(1 << 12)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 4fb6ccd..95ae40ac 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -594,14 +594,14 @@ set_hcr:
 	cmp	x0, #1
 	b.ne	3f
 
-	mrs_s	x0, ICC_SRE_EL2
+	mrs_s	x0, SYS_ICC_SRE_EL2
 	orr	x0, x0, #ICC_SRE_EL2_SRE	// Set ICC_SRE_EL2.SRE==1
 	orr	x0, x0, #ICC_SRE_EL2_ENABLE	// Set ICC_SRE_EL2.Enable==1
-	msr_s	ICC_SRE_EL2, x0
+	msr_s	SYS_ICC_SRE_EL2, x0
 	isb					// Make sure SRE is now set
-	mrs_s	x0, ICC_SRE_EL2			// Read SRE back,
+	mrs_s	x0, SYS_ICC_SRE_EL2		// Read SRE back,
 	tbz	x0, #0, 3f			// and check that it sticks
-	msr_s	ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults
+	msr_s	SYS_ICH_HCR_EL2, xzr		// Reset ICC_HCR_EL2 to defaults
 
 3:
 #endif
-- 
2.9.0

  parent reply	other threads:[~2017-04-23 17:08 UTC|newest]

Thread overview: 163+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-23 17:08 [PULL 00/79] KVM/ARM Changes for v4.12 Christoffer Dall
2017-04-23 17:08 ` Christoffer Dall
2017-04-23 17:08 ` [PULL 01/79] arm64: sysreg: sort by encoding Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 02/79] arm64: sysreg: add debug system registers Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 03/79] arm64: sysreg: add performance monitor registers Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` Christoffer Dall [this message]
2017-04-23 17:08   ` [PULL 04/79] arm64: sysreg: subsume GICv3 sysreg definitions Christoffer Dall
2017-04-23 17:08 ` [PULL 05/79] arm64: sysreg: add physical timer registers Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 06/79] arm64: sysreg: add register encodings used by KVM Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 07/79] arm64: sysreg: add Set/Way sys encodings Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 08/79] KVM: arm64: add SYS_DESC() Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 09/79] KVM: arm64: Use common debug sysreg definitions Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 10/79] KVM: arm64: Use common performance monitor " Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 11/79] KVM: arm64: Use common GICv3 " Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 12/79] KVM: arm64: Use common physical timer " Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 13/79] KVM: arm64: use common invariant " Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 14/79] KVM: arm64: Use common " Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 15/79] KVM: arm64: Use common Set/Way sys definitions Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 16/79] kvm: arm/arm64: Rework gpa callback handlers Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 17/79] KVM: arm/arm64: vgic: Defer touching GICH_VMCR to vcpu_load/put Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 18/79] KVM: arm/arm64: vgic: Avoid flushing vgic state when there's no pending IRQ Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 19/79] KVM: arm/arm64: vgic: Get rid of live_lrs Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 20/79] KVM: arm/arm64: vgic: Only set underflow when actually out of LRs Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 21/79] KVM: arm/arm64: vgic: Get rid of unnecessary process_maintenance operation Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 22/79] KVM: arm/arm64: vgic: Get rid of unnecessary save_maint_int_state Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 23/79] KVM: arm/arm64: vgic: Get rid of MISR and EISR fields Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 24/79] KVM: arm/arm64: vgic: Implement early VGIC init functionality Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 25/79] KVM: arm/arm64: vgic: Don't check vgic_initialized in sync/flush Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 26/79] KVM: arm/arm64: vgic: Improve sync_hwstate performance Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 27/79] arm64: KVM: PMU: Refactor pmu_*_el0_disabled Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 28/79] arm64: KVM: PMU: Inject UNDEF exception on illegal register access Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 29/79] arm64: KVM: PMU: Inject UNDEF on non-privileged accesses Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 30/79] arm64: KVM: Make unexpected reads from WO registers inject an undef Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 31/79] arm64: KVM: PMU: Inject UNDEF on read access to PMSWINC_EL0 Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 32/79] arm64: KVM: Treat sysreg accessors returning false as successful Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 33/79] arm64: KVM: Do not corrupt registers on failed 64bit CP read Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 34/79] arm: KVM: Make unexpected register accesses inject an undef Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 35/79] arm: KVM: Treat CP15 accessors returning false as successful Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 36/79] arm64: hyp-stub: Stop pointlessly clobbering lr Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 37/79] arm64: KVM: Move lr save/restore to do_el2_call Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 38/79] arm64: hyp-stub: Don't save lr in the EL1 code Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 39/79] arm64: hyp-stub: Define a return value for failed stub calls Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 40/79] arm64: hyp-stub: Update documentation in asm/virt.h Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 41/79] arm64: hyp-stub: Implement HVC_RESET_VECTORS stub hypercall Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 42/79] arm64: KVM: Implement HVC_RESET_VECTORS stub hypercall in the init code Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 43/79] arm64: KVM: Implement HVC_GET_VECTORS " Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 44/79] arm64: KVM: Allow the main HYP code to use the init hyp stub implementation Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 45/79] arm64: KVM: Convert __cpu_reset_hyp_mode to using __hyp_reset_vectors Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 46/79] arm64: KVM: Implement HVC_SOFT_RESTART in the init code Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 47/79] ARM: hyp-stub: improve ABI Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 48/79] ARM: soft-reboot into same mode that we entered the kernel Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:08 ` [PULL 49/79] ARM: KVM: Convert KVM to use HVC_GET_VECTORS Christoffer Dall
2017-04-23 17:08   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 50/79] ARM: Update cpu_v7_reset documentation Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 51/79] ARM: hyp-stub: Use r1 for the soft-restart address Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 52/79] ARM: Expose the VA/IDMAP offset Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 53/79] ARM: hyp-stub: Define a return value for failed stub calls Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 54/79] ARM: hyp-stub: Implement HVC_RESET_VECTORS stub hypercall Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 55/79] ARM: KVM: Implement HVC_RESET_VECTORS stub hypercall in the init code Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 56/79] ARM: KVM: Implement HVC_GET_VECTORS " Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 57/79] ARM: KVM: Allow the main HYP code to use the init hyp stub implementation Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 58/79] ARM: KVM: Convert __cpu_reset_hyp_mode to using __hyp_reset_vectors Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 59/79] ARM: KVM: Implement HVC_SOFT_RESTART in the init code Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 60/79] ARM: KVM: Gracefully handle hyp-stubs being restored from under our feet Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 61/79] arm/arm64: KVM: Use __hyp_reset_vectors() directly Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 62/79] arm/arm64: KVM: Remove kvm_get_idmap_start Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 63/79] arm/arm64: KVM: Use HVC_RESET_VECTORS to reinit HYP mode Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 64/79] ARM: decompressor: Remove __hyp_get_vectors usage Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 65/79] ARM: hyp-stub/KVM: Kill __hyp_get_vectors Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 66/79] arm64: " Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 67/79] arm64: hyp-stub: Zero x0 on successful stub handling Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 68/79] ARM: hyp-stub: Zero r0 " Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 69/79] arm/arm64: Add hyp-stub API documentation Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 70/79] KVM: arm/arm64: Cleanup the arch timer code's irqchip checking Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 71/79] KVM: arm/arm64: Add ARM user space interrupt signaling ABI Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 72/79] KVM: arm/arm64: Support arch timers with a userspace gic Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 73/79] KVM: arm/arm64: Report PMU overflow interrupts to userspace irqchip Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 74/79] KVM: arm/arm64: Advertise support for KVM_CAP_ARM_USER_IRQ Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 75/79] KVM: arm/arm64: fix races in kvm_psci_vcpu_on Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 76/79] KVM: arm/arm64: vgic-v3: De-optimize VMCR save/restore when emulating a GICv2 Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 77/79] KVM: arm/arm64: vgic-v3: Fix off-by-one LR access Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 78/79] ARM: hyp-stub: Fix Thumb-2 compilation Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-23 17:09 ` [PULL 79/79] ARM: KVM: Fix idmap stub entry when running Thumb-2 code Christoffer Dall
2017-04-23 17:09   ` Christoffer Dall
2017-04-27 15:34 ` [PULL 00/79] KVM/ARM Changes for v4.12 Paolo Bonzini
2017-04-27 15:34   ` Paolo Bonzini

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