Re: [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC

From: Stefan Hajnoczi <stefanha@gmail.com>
To: Stafford Horne <shorne@gmail.com>
Cc: QEMU Development <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC
Date: Fri, 5 May 2017 16:29:39 +0100	[thread overview]
Message-ID: <20170505152939.GF14316@stefanha-x1.localdomain> (raw)
In-Reply-To: <cover.1493858877.git.shorne@gmail.com>

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On Thu, May 04, 2017 at 09:53:15AM +0900, Stafford Horne wrote:
> Hello,
> 
> This are the openrisc patches I have been circulating on the mailing list
> of the last few months.  We have had help from a few new people and added
> the following:
>  * Fixes for gdb memory debugging
>  * Added support for Shadow Registers, EVBAR, EPH
>  * Added support for idle state, no more 100% pegged cpu's
>  * Fixed VM state persisting
> 
> 
> Changes Since v1:
>   o Fixed all checkpatch warnings and errors
> 
> 
> The following changes since commit 359c41abe32638adad503e386969fa428cecff52:
> 
>   Update version for v2.9.0 release (2017-04-20 15:31:34 +0100)
> 
> are available in the git repository at:
> 
>   git://github.com/stffrdhrn/qemu.git tags/pull-or-20170504
> 
> for you to fetch changes up to f4d1414a9385e3375d9107b29eeb75d27daf2147:
> 
>   target/openrisc: Support non-busy idle state using PMR SPR (2017-05-04 09:39:14 +0900)
> 
> ----------------------------------------------------------------
> Openrisc Features and Fixes for qemu 2.10
> 
> ----------------------------------------------------------------
> Stafford Horne (9):
>       MAINTAINERS: Add myself as openrisc maintainer
>       target/openrisc: Fixes for memory debugging
>       target/openrisc: add numcores and coreid support
>       migration: Add VMSTATE_UINTTL_2DARRAY()
>       target/openrisc: implement shadow registers
>       migration: Add VMSTATE_STRUCT_2DARRAY()
>       target/openrisc: Implement full vmstate serialization
>       target/openrisc: Remove duplicate features property
>       target/openrisc: Support non-busy idle state using PMR SPR
> 
> Tim 'mithro' Ansell (2):
>       target/openrisc: Implement EVBAR register
>       target/openrisc: Implement EPH bit
> 
>  MAINTAINERS                         |  4 +-
>  hw/openrisc/cputimer.c              |  1 +
>  include/migration/cpu.h             |  7 ++++
>  include/migration/vmstate.h         | 18 +++++++++
>  linux-user/elfload.c                |  2 +-
>  linux-user/main.c                   | 18 ++++-----
>  linux-user/openrisc/target_cpu.h    |  6 +--
>  linux-user/openrisc/target_signal.h |  2 +-
>  linux-user/signal.c                 | 17 +++++----
>  target/openrisc/cpu.c               | 16 +++-----
>  target/openrisc/cpu.h               | 46 ++++++++++++++--------
>  target/openrisc/gdbstub.c           |  4 +-
>  target/openrisc/interrupt.c         | 11 +++++-
>  target/openrisc/machine.c           | 76 +++++++++++++++++++++++++++++++++++--
>  target/openrisc/mmu.c               | 24 ++++++++++--
>  target/openrisc/sys_helper.c        | 35 +++++++++++++++++
>  target/openrisc/translate.c         |  5 ++-
>  17 files changed, 230 insertions(+), 62 deletions(-)
> 
> -- 
> 2.9.3
> 

Thanks, applied to my staging tree:
https://github.com/stefanha/qemu/commits/staging

Stefan

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