From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Stefan Hajnoczi <stefanha@gmail.com>, Stafford Horne <shorne@gmail.com>
Subject: [Qemu-devel] [PULL v2 06/11] migration: Add VMSTATE_UINTTL_2DARRAY()
Date: Thu, 4 May 2017 09:53:21 +0900 [thread overview]
Message-ID: <4597992f624c015ceb51fedb4628b3fdb1e5bbaa.1493858877.git.shorne@gmail.com> (raw)
In-Reply-To: <cover.1493858877.git.shorne@gmail.com>
In-Reply-To: <cover.1493858877.git.shorne@gmail.com>
In openRISC we are implementing the shadow registers as a 2d array.
Using this target long method rather than direct 32-bit alternatives is
consistent with the rest of our vm state serialization logic.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
include/migration/cpu.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/migration/cpu.h b/include/migration/cpu.h
index f3d5dfc..a40bd35 100644
--- a/include/migration/cpu.h
+++ b/include/migration/cpu.h
@@ -18,6 +18,8 @@
VMSTATE_UINT64_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \
+ VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, _v)
#define VMSTATE_UINTTL_TEST(_f, _s, _t) \
VMSTATE_UINT64_TEST(_f, _s, _t)
#define vmstate_info_uinttl vmstate_info_uint64
@@ -37,6 +39,8 @@
VMSTATE_UINT32_EQUAL_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, _v) \
+ VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, _v)
#define VMSTATE_UINTTL_TEST(_f, _s, _t) \
VMSTATE_UINT32_TEST(_f, _s, _t)
#define vmstate_info_uinttl vmstate_info_uint32
@@ -48,5 +52,8 @@
VMSTATE_UINTTL_EQUAL_V(_f, _s, 0)
#define VMSTATE_UINTTL_ARRAY(_f, _s, _n) \
VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_UINTTL_2DARRAY(_f, _s, _n1, _n2) \
+ VMSTATE_UINTTL_2DARRAY_V(_f, _s, _n1, _n2, 0)
+
#endif
--
2.9.3
next prev parent reply other threads:[~2017-05-04 0:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-04 0:53 [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 01/11] MAINTAINERS: Add myself as openrisc maintainer Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 02/11] target/openrisc: Implement EVBAR register Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 03/11] target/openrisc: Implement EPH bit Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 04/11] target/openrisc: Fixes for memory debugging Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 05/11] target/openrisc: add numcores and coreid support Stafford Horne
2017-05-04 0:53 ` Stafford Horne [this message]
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 07/11] target/openrisc: implement shadow registers Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 08/11] migration: Add VMSTATE_STRUCT_2DARRAY() Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 09/11] target/openrisc: Implement full vmstate serialization Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 10/11] target/openrisc: Remove duplicate features property Stafford Horne
2017-05-04 0:53 ` [Qemu-devel] [PULL v2 11/11] target/openrisc: Support non-busy idle state using PMR SPR Stafford Horne
2017-05-05 15:29 ` [Qemu-devel] [PULL v2 00/11] Fixes and features for OpenRISC Stefan Hajnoczi
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