From: Dong Aisheng <dongas86@gmail.com>
To: Stephen Boyd <sboyd@codeaurora.org>
Cc: Dong Aisheng <aisheng.dong@nxp.com>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, mturquette@baylibre.com,
shawnguo@kernel.org, Anson.Huang@nxp.com, ping.bai@nxp.com
Subject: Re: [PATCH 9/9] clk: imx: add imx7ulp clk driver
Date: Tue, 20 Jun 2017 17:42:56 +0800 [thread overview]
Message-ID: <20170620094256.GF6805@b29396-OptiPlex-7040> (raw)
In-Reply-To: <20170620020119.GQ4493@codeaurora.org>
On Mon, Jun 19, 2017 at 07:01:19PM -0700, Stephen Boyd wrote:
> On 05/15, Dong Aisheng wrote:
> > +
> > + clks[IMX7ULP_CLK_VIU] = imx_clk_gate("viu", "nic1_clk", base + 0xA0, 30);
> > + clks[IMX7ULP_CLK_PCTLC] = imx_clk_gate("pctlc", "nic1_bus_clk", base + 0xB8, 30);
> > + clks[IMX7ULP_CLK_PCTLD] = imx_clk_gate("pctld", "nic1_bus_clk", base + 0xBC, 30);
> > + clks[IMX7ULP_CLK_PCTLE] = imx_clk_gate("pctle", "nic1_bus_clk", base + 0xc0, 30);
> > + clks[IMX7ULP_CLK_PCTLF] = imx_clk_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30);
> > +
> > + clks[IMX7ULP_CLK_GPU3D] = imx_clk_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140);
> > + clks[IMX7ULP_CLK_GPU2D] = imx_clk_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144);
> > +
> > + imx_check_clocks(clks, ARRAY_SIZE(clks));
> > +
> > + clk_data.clks = clks;
> > + clk_data.clk_num = ARRAY_SIZE(clks);
> > + of_clk_add_provider(scg_node, of_clk_src_onecell_get, &clk_data);
>
> Please use of_clk_add_hw_provider() instead, and the associated
> clk_hw registration APIs.
>
Sure, will do it.
> > +
> > + pr_info("i.MX7ULP clock tree init done.\n");
>
> pr_debug?
>
Yes
> > +}
> > +
> > +CLK_OF_DECLARE(imx7ulp, "fsl,imx7ulp-clock", imx7ulp_clocks_init);
> >
>
> Any reason why it can't be a platform driver? If not, please add
> some comment explaining why.
>
Timer is using it at early stage. GIC seems not although standard
binding claim possible clock requirement.
Others still not sure.
What your suggestion?
Convert timer to platform driver and make clock as platform driver as well?
Regards
Dong Aisheng
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
WARNING: multiple messages have this Message-ID (diff)
From: dongas86@gmail.com (Dong Aisheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 9/9] clk: imx: add imx7ulp clk driver
Date: Tue, 20 Jun 2017 17:42:56 +0800 [thread overview]
Message-ID: <20170620094256.GF6805@b29396-OptiPlex-7040> (raw)
In-Reply-To: <20170620020119.GQ4493@codeaurora.org>
On Mon, Jun 19, 2017 at 07:01:19PM -0700, Stephen Boyd wrote:
> On 05/15, Dong Aisheng wrote:
> > +
> > + clks[IMX7ULP_CLK_VIU] = imx_clk_gate("viu", "nic1_clk", base + 0xA0, 30);
> > + clks[IMX7ULP_CLK_PCTLC] = imx_clk_gate("pctlc", "nic1_bus_clk", base + 0xB8, 30);
> > + clks[IMX7ULP_CLK_PCTLD] = imx_clk_gate("pctld", "nic1_bus_clk", base + 0xBC, 30);
> > + clks[IMX7ULP_CLK_PCTLE] = imx_clk_gate("pctle", "nic1_bus_clk", base + 0xc0, 30);
> > + clks[IMX7ULP_CLK_PCTLF] = imx_clk_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30);
> > +
> > + clks[IMX7ULP_CLK_GPU3D] = imx_clk_composite("gpu3d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140);
> > + clks[IMX7ULP_CLK_GPU2D] = imx_clk_composite("gpu2d", periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144);
> > +
> > + imx_check_clocks(clks, ARRAY_SIZE(clks));
> > +
> > + clk_data.clks = clks;
> > + clk_data.clk_num = ARRAY_SIZE(clks);
> > + of_clk_add_provider(scg_node, of_clk_src_onecell_get, &clk_data);
>
> Please use of_clk_add_hw_provider() instead, and the associated
> clk_hw registration APIs.
>
Sure, will do it.
> > +
> > + pr_info("i.MX7ULP clock tree init done.\n");
>
> pr_debug?
>
Yes
> > +}
> > +
> > +CLK_OF_DECLARE(imx7ulp, "fsl,imx7ulp-clock", imx7ulp_clocks_init);
> >
>
> Any reason why it can't be a platform driver? If not, please add
> some comment explaining why.
>
Timer is using it at early stage. GIC seems not although standard
binding claim possible clock requirement.
Others still not sure.
What your suggestion?
Convert timer to platform driver and make clock as platform driver as well?
Regards
Dong Aisheng
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
> --
> To unsubscribe from this list: send the line "unsubscribe linux-clk" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2017-06-20 9:44 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-15 13:59 [PATCH 0/9] clk: add imx7ulp clk support Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-05-15 13:59 ` [PATCH 1/9] clk: clk-divider: add CLK_DIVIDER_ZERO_GATE " Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-06-20 1:45 ` Stephen Boyd
2017-06-20 1:45 ` Stephen Boyd
2017-06-20 9:08 ` Dong Aisheng
2017-06-20 9:08 ` Dong Aisheng
2017-06-26 3:07 ` A.s. Dong
2017-06-26 3:07 ` A.s. Dong
2017-06-26 3:07 ` A.s. Dong
2017-07-01 0:55 ` Stephen Boyd
2017-07-01 0:55 ` Stephen Boyd
2017-07-03 3:46 ` A.s. Dong
2017-07-03 3:46 ` A.s. Dong
2017-07-03 3:46 ` A.s. Dong
2017-05-15 13:59 ` [PATCH 2/9] clk: reparent orphans after critical clocks enabled Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-06-20 1:51 ` Stephen Boyd
2017-06-20 1:51 ` Stephen Boyd
2017-06-20 9:25 ` Dong Aisheng
2017-06-20 9:25 ` Dong Aisheng
2017-05-15 13:59 ` [PATCH 3/9] clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-06-20 1:55 ` Stephen Boyd
2017-06-20 1:55 ` Stephen Boyd
2017-06-20 9:26 ` Dong Aisheng
2017-06-20 9:26 ` Dong Aisheng
2017-05-15 13:59 ` [PATCH 4/9] clk: imx: add pllv4 support Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-06-20 1:59 ` Stephen Boyd
2017-06-20 1:59 ` Stephen Boyd
2017-06-20 9:31 ` Dong Aisheng
2017-06-20 9:31 ` Dong Aisheng
2017-07-01 0:36 ` Stephen Boyd
2017-07-01 0:36 ` Stephen Boyd
2017-07-03 3:21 ` A.s. Dong
2017-07-03 3:21 ` A.s. Dong
2017-07-03 3:21 ` A.s. Dong
2017-05-15 13:59 ` [PATCH 5/9] clk: imx: add pfdv2 support Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-05-15 13:59 ` [PATCH 6/9] clk: imx: add composite clk support Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-06-20 2:00 ` Stephen Boyd
2017-06-20 2:00 ` Stephen Boyd
2017-06-20 9:32 ` Dong Aisheng
2017-06-20 9:32 ` Dong Aisheng
2017-05-15 13:59 ` [PATCH 7/9] dt-bindings: clock: add imx7ulp clock binding doc Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-05-15 13:59 ` [PATCH 8/9] clk: imx: make mux parent strings const Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-06-20 2:01 ` Stephen Boyd
2017-06-20 2:01 ` Stephen Boyd
2017-05-15 13:59 ` [PATCH 9/9] clk: imx: add imx7ulp clk driver Dong Aisheng
2017-05-15 13:59 ` Dong Aisheng
2017-06-20 2:01 ` Stephen Boyd
2017-06-20 2:01 ` Stephen Boyd
2017-06-20 9:42 ` Dong Aisheng [this message]
2017-06-20 9:42 ` Dong Aisheng
2017-06-20 20:41 ` Stephen Boyd
2017-06-20 20:41 ` Stephen Boyd
2017-06-21 7:13 ` A.s. Dong
2017-06-21 7:13 ` A.s. Dong
2017-06-21 7:13 ` A.s. Dong
2017-07-01 0:35 ` Stephen Boyd
2017-07-01 0:35 ` Stephen Boyd
2017-07-01 0:35 ` Stephen Boyd
2017-07-03 3:18 ` A.s. Dong
2017-07-03 3:18 ` A.s. Dong
2017-07-03 3:18 ` A.s. Dong
2017-06-13 6:42 ` [PATCH 0/9] clk: add imx7ulp clk support Dong Aisheng
2017-06-13 6:42 ` Dong Aisheng
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