From: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
To: Michael Turquette
<mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>,
Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>,
Srinivas Kandagatla
<srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Ian Campbell
<ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>,
Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Romain Perier
<romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
Subject: [PATCH 2/4] clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
Date: Mon, 28 Aug 2017 14:16:02 +0200 [thread overview]
Message-ID: <20170828121604.15968-3-romain.perier@collabora.com> (raw)
In-Reply-To: <20170828121604.15968-1-romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
This exports the clock for the pclk gate of the eFuse that is part of
the RK3368 SoCs. So we can use it from the dt-bindings.
Signed-off-by: Romain Perier <romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
---
drivers/clk/rockchip/clk-rk3368.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index fc56565379dd..7c4d242f19c1 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
- GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
+ GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
/*
--
2.11.0
--
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WARNING: multiple messages have this Message-ID (diff)
From: Romain Perier <romain.perier@collabora.com>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@codeaurora.org>,
linux-clk@vger.kernel.org, Heiko Stuebner <heiko@sntech.de>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Cc: devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Kumar Gala <galak@codeaurora.org>,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
Romain Perier <romain.perier@collabora.com>
Subject: [PATCH 2/4] clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
Date: Mon, 28 Aug 2017 14:16:02 +0200 [thread overview]
Message-ID: <20170828121604.15968-3-romain.perier@collabora.com> (raw)
In-Reply-To: <20170828121604.15968-1-romain.perier@collabora.com>
This exports the clock for the pclk gate of the eFuse that is part of
the RK3368 SoCs. So we can use it from the dt-bindings.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
drivers/clk/rockchip/clk-rk3368.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index fc56565379dd..7c4d242f19c1 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
- GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
+ GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
/*
--
2.11.0
WARNING: multiple messages have this Message-ID (diff)
From: romain.perier@collabora.com (Romain Perier)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/4] clk: rockchip: export clock pclk_efuse_256 for RK3368 SoCs
Date: Mon, 28 Aug 2017 14:16:02 +0200 [thread overview]
Message-ID: <20170828121604.15968-3-romain.perier@collabora.com> (raw)
In-Reply-To: <20170828121604.15968-1-romain.perier@collabora.com>
This exports the clock for the pclk gate of the eFuse that is part of
the RK3368 SoCs. So we can use it from the dt-bindings.
Signed-off-by: Romain Perier <romain.perier@collabora.com>
---
drivers/clk/rockchip/clk-rk3368.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index fc56565379dd..7c4d242f19c1 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -711,7 +711,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
- GATE(0, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
+ GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
/*
--
2.11.0
next prev parent reply other threads:[~2017-08-28 12:16 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-28 12:16 [PATCH 0/4] rockchip: Add efuse support for RK3368 SoCs Romain Perier
2017-08-28 12:16 ` Romain Perier
2017-08-28 12:16 ` Romain Perier
[not found] ` <20170828121604.15968-1-romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2017-08-28 12:16 ` [PATCH 1/4] clk: rockchip: add clock id for PCLK_EFUSE256 of " Romain Perier
2017-08-28 12:16 ` Romain Perier
2017-08-28 12:16 ` Romain Perier
2017-08-28 12:16 ` Romain Perier [this message]
2017-08-28 12:16 ` [PATCH 2/4] clk: rockchip: export clock pclk_efuse_256 for " Romain Perier
2017-08-28 12:16 ` Romain Perier
2017-08-28 12:16 ` [PATCH 4/4] arm64: dts: rockchip: add efuse " Romain Perier
2017-08-28 12:16 ` Romain Perier
2017-08-28 12:16 ` Romain Perier
2017-08-28 12:16 ` [PATCH 3/4] nvmem: rockchip: add support for RK3368 Romain Perier
2017-08-28 12:16 ` Romain Perier
2017-08-28 12:42 ` Heiko Stübner
2017-08-28 12:42 ` Heiko Stübner
[not found] ` <20170828121604.15968-4-romain.perier-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
2017-08-28 15:12 ` [3/4] " Philipp Tomsich
2017-08-28 15:12 ` Philipp Tomsich
2017-08-28 15:12 ` Philipp Tomsich
2017-09-01 14:32 ` [PATCH 3/4] " Rob Herring
2017-09-01 14:32 ` Rob Herring
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