From: Ross Zwisler <ross.zwisler@linux.intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-nvdimm <linux-nvdimm@lists.01.org>
Subject: Re: [PATCH v2 3/3] libnvdimm: don't flush power-fail protected CPU caches
Date: Wed, 6 Jun 2018 09:30:59 -0600 [thread overview]
Message-ID: <20180606153059.GA30568@linux.intel.com> (raw)
In-Reply-To: <CAPcyv4gs-EMxQhX6dNYnygav1RfaLOuuA0XwYVHv-eSirjw6jA@mail.gmail.com>
On Tue, Jun 05, 2018 at 07:00:14PM -0700, Dan Williams wrote:
> On Tue, Jun 5, 2018 at 4:58 PM, Ross Zwisler
> <ross.zwisler@linux.intel.com> wrote:
> > This commit:
> >
> > 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
> >
> > intended to make sure that deep flush was always available even on
> > platforms which support a power-fail protected CPU cache. An unintended
> > side effect of this change was that we also lost the ability to skip
> > flushing CPU caches on those power-fail protected CPU cache.
> >
> > Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
> > Fixes: 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
> > ---
> > drivers/dax/super.c | 14 +++++++++++++-
> > drivers/nvdimm/pmem.c | 2 ++
> > include/linux/dax.h | 4 ++++
> > 3 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/dax/super.c b/drivers/dax/super.c
> > index c2c46f96b18c..80253c531a9b 100644
> > --- a/drivers/dax/super.c
> > +++ b/drivers/dax/super.c
> > @@ -152,6 +152,8 @@ enum dax_device_flags {
> > DAXDEV_ALIVE,
> > /* gate whether dax_flush() calls the low level flush routine */
> > DAXDEV_WRITE_CACHE,
> > + /* only flush the CPU caches if they are not power fail protected */
> > + DAXDEV_FLUSH_ON_SYNC,
>
> I'm not grokking why we need DAXDEV_FLUSH_ON_SYNC. The power fail
> protected status of the cache only determines the default for
> DAXDEV_WRITE_CACHE.
Ah, yea, that's much cleaner. I'll send out a v3.
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WARNING: multiple messages have this Message-ID (diff)
From: Ross Zwisler <ross.zwisler@linux.intel.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Ross Zwisler <ross.zwisler@linux.intel.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Dave Jiang <dave.jiang@intel.com>,
linux-nvdimm <linux-nvdimm@lists.01.org>
Subject: Re: [PATCH v2 3/3] libnvdimm: don't flush power-fail protected CPU caches
Date: Wed, 6 Jun 2018 09:30:59 -0600 [thread overview]
Message-ID: <20180606153059.GA30568@linux.intel.com> (raw)
In-Reply-To: <CAPcyv4gs-EMxQhX6dNYnygav1RfaLOuuA0XwYVHv-eSirjw6jA@mail.gmail.com>
On Tue, Jun 05, 2018 at 07:00:14PM -0700, Dan Williams wrote:
> On Tue, Jun 5, 2018 at 4:58 PM, Ross Zwisler
> <ross.zwisler@linux.intel.com> wrote:
> > This commit:
> >
> > 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
> >
> > intended to make sure that deep flush was always available even on
> > platforms which support a power-fail protected CPU cache. An unintended
> > side effect of this change was that we also lost the ability to skip
> > flushing CPU caches on those power-fail protected CPU cache.
> >
> > Signed-off-by: Ross Zwisler <ross.zwisler@linux.intel.com>
> > Fixes: 5fdf8e5ba566 ("libnvdimm: re-enable deep flush for pmem devices via fsync()")
> > ---
> > drivers/dax/super.c | 14 +++++++++++++-
> > drivers/nvdimm/pmem.c | 2 ++
> > include/linux/dax.h | 4 ++++
> > 3 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/dax/super.c b/drivers/dax/super.c
> > index c2c46f96b18c..80253c531a9b 100644
> > --- a/drivers/dax/super.c
> > +++ b/drivers/dax/super.c
> > @@ -152,6 +152,8 @@ enum dax_device_flags {
> > DAXDEV_ALIVE,
> > /* gate whether dax_flush() calls the low level flush routine */
> > DAXDEV_WRITE_CACHE,
> > + /* only flush the CPU caches if they are not power fail protected */
> > + DAXDEV_FLUSH_ON_SYNC,
>
> I'm not grokking why we need DAXDEV_FLUSH_ON_SYNC. The power fail
> protected status of the cache only determines the default for
> DAXDEV_WRITE_CACHE.
Ah, yea, that's much cleaner. I'll send out a v3.
next prev parent reply other threads:[~2018-06-06 15:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-05 23:58 [PATCH v2 1/3] libnvdimm: unconditionally deep flush on *sync Ross Zwisler
2018-06-05 23:58 ` Ross Zwisler
2018-06-05 23:58 ` [PATCH v2 2/3] libnvdimm: use dax_write_cache* helpers Ross Zwisler
2018-06-05 23:58 ` Ross Zwisler
2018-06-05 23:58 ` [PATCH v2 3/3] libnvdimm: don't flush power-fail protected CPU caches Ross Zwisler
2018-06-05 23:58 ` Ross Zwisler
2018-06-06 2:00 ` Dan Williams
2018-06-06 2:00 ` Dan Williams
2018-06-06 15:30 ` Ross Zwisler [this message]
2018-06-06 15:30 ` Ross Zwisler
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