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From: David Gibson <david@gibson.dropbear.id.au>
To: peter.maydell@linaro.org
Cc: agraf@suse.de, aik@ozlabs.ru, groug@kaod.org, clg@kaod.org,
	lvivier@redhat.com, qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
	David Gibson <david@gibson.dropbear.id.au>
Subject: [Qemu-devel] [PATCH 06/23] ppc/pnv: consolidate the creation of the ISA bus device tree
Date: Fri, 22 Jun 2018 14:24:20 +1000	[thread overview]
Message-ID: <20180622042437.14259-6-david@gibson.dropbear.id.au> (raw)
In-Reply-To: <20180622042437.14259-1-david@gibson.dropbear.id.au>

From: Cédric Le Goater <clg@kaod.org>

The device tree node of the ISA bus was being partially done in
different places. Move all the nodes creation under the same routine.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/pnv.c | 51 +++++++++++++++++++++++----------------------------
 1 file changed, 23 insertions(+), 28 deletions(-)

diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index a29ea996b4..7401ffe5b0 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -265,18 +265,6 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
     g_free(reg);
 }
 
-static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt)
-{
-    char *name;
-    int offset;
-
-    name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
-                           (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE);
-    offset = fdt_path_offset(fdt, name);
-    g_free(name);
-    return offset;
-}
-
 static void pnv_dt_chip(PnvChip *chip, void *fdt)
 {
     const char *typename = pnv_chip_core_typename(chip);
@@ -285,16 +273,6 @@ static void pnv_dt_chip(PnvChip *chip, void *fdt)
 
     pnv_dt_xscom(chip, fdt, 0);
 
-    /* The default LPC bus of a multichip system is on chip 0. It's
-     * recognized by the firmware (skiboot) using a "primary"
-     * property.
-     */
-    if (chip->chip_id == 0x0) {
-        int lpc_offset = pnv_chip_lpc_offset(chip, fdt);
-
-        _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0)));
-    }
-
     for (i = 0; i < chip->nr_cores; i++) {
         PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
 
@@ -418,16 +396,35 @@ static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
     return 0;
 }
 
-static void pnv_dt_isa(ISABus *bus, void *fdt, int lpc_offset)
+static int pnv_chip_isa_offset(PnvChip *chip, void *fdt)
+{
+    char *name;
+    int offset;
+
+    name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
+                           (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE);
+    offset = fdt_path_offset(fdt, name);
+    g_free(name);
+    return offset;
+}
+
+/* The default LPC bus of a multichip system is on chip 0. It's
+ * recognized by the firmware (skiboot) using a "primary" property.
+ */
+static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
 {
+    int isa_offset = pnv_chip_isa_offset(pnv->chips[0], fdt);
     ForeachPopulateArgs args = {
         .fdt = fdt,
-        .offset = lpc_offset,
+        .offset = isa_offset,
     };
 
+    _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
+
     /* ISA devices are not necessarily parented to the ISA bus so we
      * can not use object_child_foreach() */
-    qbus_walk_children(BUS(bus), pnv_dt_isa_device, NULL, NULL, NULL, &args);
+    qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
+                       &args);
 }
 
 static void *pnv_dt_create(MachineState *machine)
@@ -438,7 +435,6 @@ static void *pnv_dt_create(MachineState *machine)
     char *buf;
     int off;
     int i;
-    int lpc_offset;
 
     fdt = g_malloc0(FDT_MAX_SIZE);
     _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
@@ -480,8 +476,7 @@ static void *pnv_dt_create(MachineState *machine)
     }
 
     /* Populate ISA devices on chip 0 */
-    lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt);
-    pnv_dt_isa(pnv->isa_bus, fdt, lpc_offset);
+    pnv_dt_isa(pnv, fdt);
 
     if (pnv->bmc) {
         pnv_dt_bmc_sensors(pnv->bmc, fdt);
-- 
2.17.1

  parent reply	other threads:[~2018-06-22  4:24 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-22  4:24 [Qemu-devel] [PATCH 01/23] ppc/pnv: introduce a new intc_create() operation to the chip model David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 02/23] ppc/pnv: introduce a new isa_create() " David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 03/23] spapr_cpu_core: migrate per-CPU data David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 04/23] spapr_cpu_core: migrate VPA related state David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 05/23] ppc/pnv: introduce Pnv8Chip and Pnv9Chip models David Gibson
2018-06-22  4:24 ` David Gibson [this message]
2018-06-22  4:24 ` [Qemu-devel] [PATCH 07/23] target/ppc: Allow cpu compatiblity checks based on type, not instance David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 08/23] spapr: Compute effective capability values earlier David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 09/23] spapr: Add cpu_apply hook to capabilities David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 10/23] target/ppc: Add kvmppc_hpt_needs_host_contiguous_pages() helper David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 11/23] spapr: split the IRQ allocation sequence David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 12/23] spapr: remove unused spapr_irq routines David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 13/23] fpu_helper.c: fix helper_fpscr_clrbit() function David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 14/23] sm501: Fix hardware cursor color conversion David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 15/23] ppc4xx_i2c: Remove unimplemented sdata and intr registers David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 16/23] ppc4xx_i2c: Implement directcntl register David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 17/23] target/ppc: Add missing opcode for icbt on PPC440 David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 18/23] pseries: Update SLOF firmware image to qemu-slof-20180621 David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 19/23] spapr: Maximum (HPT) pagesize property David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 20/23] spapr: Use maximum page size capability to simplify memory backend checking David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 21/23] target/ppc: Add ppc_hash64_filter_pagesizes() David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 22/23] spapr: Limit available pagesizes to provide a consistent guest environment David Gibson
2018-06-22  4:24 ` [Qemu-devel] [PATCH 23/23] spapr: Don't rewrite mmu capabilities in KVM mode David Gibson
2018-06-22  9:44 ` [Qemu-devel] [PATCH 01/23] ppc/pnv: introduce a new intc_create() operation to the chip model Greg Kurz
2018-06-22 10:32   ` David Gibson
2018-06-26  9:07 ` Peter Maydell
2018-06-26  9:31   ` Cédric Le Goater

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