From: Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
To: abhinavk-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
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jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
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Subject: [PATCH v3 19/19] drm/msm: Add SDM845 DPU support
Date: Fri, 20 Jul 2018 16:43:10 -0400 [thread overview]
Message-ID: <20180720204315.19054-20-seanpaul@chromium.org> (raw)
In-Reply-To: <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
From: Jeykumar Sankaran <jsanka@codeaurora.org>
SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a
top level wrapper consisting of Display Processing Unit (DPU) and
display peripheral modules such as Display Serial Interface (DSI)
and DisplayPort (DP).
MDSS functions essentially as a back-end composition engine. It blends
video and graphic images stored in the frame buffers and scans out the
composed image to a display sink (over DSI/DP).
The following diagram represents hardware blocks for a simple pipeline
(two planes are present on a given crtc which is connected to a DSI
connector):
MDSS
+---------------------------------+
| +-----------------------------+ |
| | DPU | |
| | +--------+ +--------+ | |
| | | SSPP | | SSPP | | |
| | +----+---+ +----+---+ | |
| | | | | |
| | +----v-----------v---+ | |
| | | Layer Mixer (LM) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | PingPong (PP) | | |
| | +--------------------+ | |
| | +--------------------+ | |
| | | INTERFACE (VIDEO) | | |
| | +---+----------------+ | |
| +------|----------------------+ |
| | |
| +------|---------------------+ |
| | | DISPLAY PERIPHERALS | |
| | +---v-+ +-----+ | |
| | | DSI | | DP | | |
| | +-----+ +-----+ | |
| +----------------------------+ |
+---------------------------------+
The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs)
depends on SoC capabilities.
Overview of DPU sub-blocks:
---------------------------
* Source Surface Processor (SSPP):
Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are
capable of performing format conversion, scaling and quality improvement
for source surfaces.
* Layer Mixer (LM):
Blend source surfaces together (in requested zorder)
* PingPong (PP):
This block controls frame done interrupt output, EOL and EOF generation,
overflow/underflow control.
* Display interface (INTF):
Timing generator and interface connecting the display peripherals.
DRM components mapping to DPU architecture:
------------------------------------------
PLANEs maps to SSPPs
CRTC maps to LMs
Encoder maps to PPs, INTFs
Data flow setup:
---------------
MDSS hardware can support various data flows (e.g.):
- Dual pipe: Output from two LMs combined to single display.
- Split display: Output from two LMs connected to two separate
interfaces.
The hardware capabilities determine the number of concurrent data paths
possible. Any control path (i.e. pipeline w/i DPU) can be routed to any
of the hardware data paths. A given control path can be triggered,
flushed and controlled independently.
Changes in v3:
- Move msm_media_info.h from uapi to dpu/ subdir
- Remove preclose callback dpu (it's handled in core)
- Fix kbuild warnings with parent_ops
- Remove unused functions from dpu_core_irq
- Rename mdss_phys to mdss
- Rename mdp_phys address space to mdp
- Drop _phys from vbif and regdma binding names
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org>
Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
---
drivers/gpu/drm/msm/Makefile | 32 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c | 479 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h | 153 +
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 637 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 133 +
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2504 ++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 484 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c | 2393 +++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h | 103 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2575 +++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 191 ++
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 453 +++
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 905 ++++++
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 922 ++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c | 1276 ++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h | 136 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c | 155 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h | 53 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 511 ++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 804 +++++
.../drm/msm/disp/dpu1/dpu_hw_catalog_format.h | 182 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c | 323 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h | 139 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 540 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 218 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 1183 ++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 257 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 349 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 128 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 261 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 122 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 465 +++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 250 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 136 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 753 +++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 424 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 398 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 202 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 452 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 358 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c | 275 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h | 128 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h | 56 +
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c | 204 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h | 57 +
drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c | 66 +
drivers/gpu/drm/msm/disp/dpu1/dpu_irq.h | 59 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1345 +++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 402 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c | 153 +
drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 245 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 1963 +++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 175 ++
.../gpu/drm/msm/disp/dpu1/dpu_power_handle.c | 249 ++
.../gpu/drm/msm/disp/dpu1/dpu_power_handle.h | 225 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 1079 +++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 199 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 1007 +++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c | 384 +++
drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h | 94 +
.../gpu/drm/msm/disp/dpu1/msm_media_info.h | 1376 +++++++++
drivers/gpu/drm/msm/msm_drv.c | 135 +-
drivers/gpu/drm/msm/msm_drv.h | 81 +-
drivers/gpu/drm/msm/msm_kms.h | 8 +
64 files changed, 31989 insertions(+), 15 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_irq.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_dbg.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_formats.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_blk.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog_format.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_io_util.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_irq.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_irq.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_kms_utils.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_power_handle.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/msm_media_info.h
The patch is too large for dri-devel, please refer to:
https://gitlab.freedesktop.org/seanpaul/dpu-staging/commit/00601828c2959f91397e938a9632741f42e994c5
--
Sean Paul, Software Engineer, Google / Chromium OS
_______________________________________________
Freedreno mailing list
Freedreno@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/freedreno
prev parent reply other threads:[~2018-07-20 20:43 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 20:42 [PATCH v3 00/19] drm/msm: Add support for SDM845 Display Processing Unit (DPU) Sean Paul
2018-07-20 20:42 ` [PATCH v3 03/19] drm: add msm compressed format modifiers Sean Paul
[not found] ` <20180720204315.19054-4-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-25 14:09 ` Stanimir Varbanov
2018-07-25 23:09 ` Jeykumar Sankaran
2018-07-26 9:37 ` Stanimir Varbanov
[not found] ` <d224e3ff142d687c07233f70864206af-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-07-26 11:45 ` Rob Clark
[not found] ` <CAF6AEGvrpmNVtYJxMR2Ka5S3_oeGm8C_SbeOPZR_TAONhS0_KA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-07-26 14:43 ` [PATCH v4 " Sean Paul
2018-07-20 20:42 ` [PATCH v3 04/19] drm/msm/dsi: adjust dsi timing for dual dsi mode Sean Paul
2018-07-20 20:42 ` [PATCH v3 06/19] drm/msm/dsi: initialize postdiv_lock before use for 10nm pll Sean Paul
2018-07-20 20:43 ` [PATCH v3 09/19] drm/msm/mdp5: subclass msm_mdss for mdp5 Sean Paul
2018-07-20 20:43 ` [PATCH v3 12/19] drm/msm: Clean up dangling atomic_wq Sean Paul
[not found] ` <20180720204315.19054-1-seanpaul-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
2018-07-20 20:42 ` [PATCH v3 01/19] dt-bindings: msm/dsi: Add mdp transfer time to msm dsi binding Sean Paul
2018-07-20 20:42 ` [PATCH v3 02/19] drm: Add support for pps and compression mode command packet Sean Paul
2018-07-20 20:42 ` Sean Paul
2018-07-20 20:42 ` Sean Paul
2018-07-20 20:42 ` [PATCH v3 05/19] drm/msm/dsi: Use one connector for dual DSI mode Sean Paul
2018-07-20 20:42 ` [PATCH v3 07/19] drm/msm/dsi: set encoder mode for DRM bridge explicitly Sean Paul
2018-07-20 20:42 ` [PATCH v3 08/19] drm/msm: Move wait_for_vblanks into mdp complete_commit() hooks Sean Paul
2018-07-20 20:43 ` [PATCH v3 10/19] drm/msm: enable zpos normalization Sean Paul
2018-07-20 20:43 ` [PATCH v3 11/19] drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor Sean Paul
2018-07-20 20:43 ` [PATCH v3 13/19] drm/msm: #define MDP version numbers Sean Paul
2018-07-20 20:43 ` [PATCH v3 14/19] drm/msm: Use labels for unwinding in the error path Sean Paul
2018-07-20 20:43 ` [PATCH v3 15/19] drm/msm: #define MAX_<OBJECT> in msm_drv.h Sean Paul
2018-07-20 20:43 ` [PATCH v3 16/19] drm/msm: Add .commit() callback to msm_kms functions Sean Paul
2018-07-20 20:43 ` [PATCH v3 17/19] drm/msm: Add pm_suspend/resume callbacks to msm_kms Sean Paul
2018-07-20 20:43 ` [PATCH v3 18/19] dt-bindings: msm/disp: Add bindings for Snapdragon 845 DPU Sean Paul
2018-07-24 23:31 ` Rob Herring
2018-07-20 20:43 ` Sean Paul [this message]
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