From: Aapo Vienamo <avienamo@nvidia.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Ulf Hansson <ulf.hansson@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>, Mikko Perttunen <mperttunen@nvidia.com>, Stefan Agner <stefan@agner.ch> Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Aapo Vienamo <avienamo@nvidia.com> Subject: [PATCH v3 19/38] mmc: tegra: Add a workaround for tap value change glitch Date: Thu, 30 Aug 2018 18:06:20 +0300 [thread overview] Message-ID: <20180830150639.21048-20-avienamo@nvidia.com> (raw) In-Reply-To: <20180830150639.21048-1-avienamo@nvidia.com> Add quirk to disable the card clock during configuration of the tap value in tegra_sdhci_set_tap() and issue sdhci_reset() after value change. This is a workaround to avoid propagation of a potential glitch caused by setting the tap value. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- drivers/mmc/host/sdhci-tegra.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index caa9a1b30d2e..d0a536f1b994 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -47,6 +47,9 @@ #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 +#define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 +#define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 + #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 #define SDHCI_AUTO_CAL_START BIT(31) #define SDHCI_AUTO_CAL_ENABLE BIT(29) @@ -68,6 +71,7 @@ #define NVQUIRK_ENABLE_DDR50 BIT(5) #define NVQUIRK_HAS_PADCALIB BIT(6) #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) +#define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) struct sdhci_tegra_soc_data { const struct sdhci_pltfm_data *pdata; @@ -515,12 +519,32 @@ static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; + bool card_clk_enabled = false; u32 reg; + /* + * Touching the tap values is a bit tricky on some SoC generations. + * The quirk enables a workaround for a glitch that sometimes occurs if + * the tap values are changed. + */ + + if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) + card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); + reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); + + if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && + card_clk_enabled) { + usleep_range(1, 2); + sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + tegra_sdhci_configure_card_clk(host, card_clk_enabled); + } } static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) @@ -774,7 +798,8 @@ static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { static const struct sdhci_tegra_soc_data soc_data_tegra210 = { .pdata = &sdhci_tegra210_pdata, .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | - NVQUIRK_HAS_PADCALIB, + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, }; static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { @@ -799,7 +824,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { static const struct sdhci_tegra_soc_data soc_data_tegra186 = { .pdata = &sdhci_tegra186_pdata, .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | - NVQUIRK_HAS_PADCALIB, + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, }; static const struct of_device_id sdhci_tegra_dt_match[] = { -- 2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Aapo Vienamo <avienamo@nvidia.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Ulf Hansson <ulf.hansson@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>, Mikko Perttunen <mperttunen@nvidia.com>, "Stefan Agner" <stefan@agner.ch> Cc: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, Aapo Vienamo <avienamo@nvidia.com> Subject: [PATCH v3 19/38] mmc: tegra: Add a workaround for tap value change glitch Date: Thu, 30 Aug 2018 18:06:20 +0300 [thread overview] Message-ID: <20180830150639.21048-20-avienamo@nvidia.com> (raw) In-Reply-To: <20180830150639.21048-1-avienamo@nvidia.com> Add quirk to disable the card clock during configuration of the tap value in tegra_sdhci_set_tap() and issue sdhci_reset() after value change. This is a workaround to avoid propagation of a potential glitch caused by setting the tap value. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- drivers/mmc/host/sdhci-tegra.c | 30 ++++++++++++++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index caa9a1b30d2e..d0a536f1b994 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -47,6 +47,9 @@ #define SDHCI_MISC_CTRL_ENABLE_SDHCI_SPEC_300 0x20 #define SDHCI_MISC_CTRL_ENABLE_DDR50 0x200 +#define SDHCI_VNDR_TUN_CTRL0_0 0x1c0 +#define SDHCI_VNDR_TUN_CTRL0_TUN_HW_TAP 0x20000 + #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 #define SDHCI_AUTO_CAL_START BIT(31) #define SDHCI_AUTO_CAL_ENABLE BIT(29) @@ -68,6 +71,7 @@ #define NVQUIRK_ENABLE_DDR50 BIT(5) #define NVQUIRK_HAS_PADCALIB BIT(6) #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) +#define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) struct sdhci_tegra_soc_data { const struct sdhci_pltfm_data *pdata; @@ -515,12 +519,32 @@ static unsigned int tegra_sdhci_get_max_clock(struct sdhci_host *host) static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; + bool card_clk_enabled = false; u32 reg; + /* + * Touching the tap values is a bit tricky on some SoC generations. + * The quirk enables a workaround for a glitch that sometimes occurs if + * the tap values are changed. + */ + + if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) + card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); + reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); reg &= ~SDHCI_CLOCK_CTRL_TAP_MASK; reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; sdhci_writel(host, reg, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); + + if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && + card_clk_enabled) { + usleep_range(1, 2); + sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); + tegra_sdhci_configure_card_clk(host, card_clk_enabled); + } } static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) @@ -774,7 +798,8 @@ static const struct sdhci_pltfm_data sdhci_tegra210_pdata = { static const struct sdhci_tegra_soc_data soc_data_tegra210 = { .pdata = &sdhci_tegra210_pdata, .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | - NVQUIRK_HAS_PADCALIB, + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, }; static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { @@ -799,7 +824,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { static const struct sdhci_tegra_soc_data soc_data_tegra186 = { .pdata = &sdhci_tegra186_pdata, .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | - NVQUIRK_HAS_PADCALIB, + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP, }; static const struct of_device_id sdhci_tegra_dt_match[] = { -- 2.18.0
next prev parent reply other threads:[~2018-08-30 15:06 UTC|newest] Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-08-30 15:06 [PATCH v3 00/38] Tegra SDHCI add support for HS200 and UHS signaling Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 01/38] dt-bindings: Add Tegra PMC pad configuration bindings Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 02/38] dt-bindings: mmc: tegra: Add pad voltage control properties Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 13:15 ` Ulf Hansson 2018-08-30 15:06 ` [PATCH v3 03/38] dt-bindings: Add Tegra SDHCI pad pdpu offset bindings Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 13:15 ` Ulf Hansson 2018-08-30 15:06 ` [PATCH v3 04/38] dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 13:15 ` Ulf Hansson 2018-08-30 15:06 ` [PATCH v3 05/38] soc/tegra: pmc: Fix pad voltage configuration for Tegra186 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 06/38] soc/tegra: pmc: Factor out DPD register bit calculation Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 07/38] soc/tegra: pmc: Implement tegra_io_pad_is_powered() Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 08/38] soc/tegra: pmc: Use X macro to generate IO pad tables Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 09/38] soc/tegra: pmc: Remove public pad voltage APIs Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 10/38] soc/tegra: pmc: Implement pad configuration via pinctrl Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 11/38] mmc: tegra: Reconfigure pad voltages during voltage switching Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 13:16 ` Ulf Hansson 2018-08-31 13:59 ` Thierry Reding 2018-08-30 15:06 ` [PATCH v3 12/38] mmc: tegra: Poll for calibration completion Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 13/38] mmc: tegra: Set calibration pad voltage reference Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 14/38] mmc: tegra: Power on the calibration pad Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 15/38] mmc: tegra: Disable card clock during pad calibration Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 16/38] mmc: tegra: Program pad autocal offsets from dt Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 17/38] mmc: tegra: Perform pad calibration after voltage switch Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 18/38] mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo [this message] 2018-08-30 15:06 ` [PATCH v3 19/38] mmc: tegra: Add a workaround for tap value change glitch Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 20/38] mmc: tegra: Parse default trim and tap from dt Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 21/38] mmc: tegra: Configure default tap values Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 22/38] mmc: tegra: Configure default trim value on reset Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 23/38] mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 24/38] mmc: tegra: Remove tegra_sdhci_writew() from tegra210_sdhci_ops Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 25/38] mmc: tegra: Disable card clock during tuning cmd on Tegra210 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 26/38] mmc: tegra: Enable UHS and HS200 modes for Tegra210 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 27/38] mmc: tegra: Enable UHS and HS200 modes for Tegra186 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 28/38] arm64: dts: Add Tegra210 sdmmc pinctrl voltage states Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 29/38] arm64: dts: Add Tegra186 " Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 30/38] arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 31/38] arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 32/38] arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 33/38] arm64: dts: tegra186: Add sdmmc pad auto calibration offsets Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 34/38] arm64: dts: tegra210: " Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 35/38] arm64: dts: tegra210: Add SDHCI tap and trim values Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 36/38] arm64: dts: tegra186: " Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 37/38] arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 38/38] arm64: dts: tegra210: " Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 7:20 ` [PATCH v3 00/38] Tegra SDHCI add support for HS200 and UHS signaling Adrian Hunter
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