From: Icenowy Zheng <icenowy@aosc.io>
To: Maxime Ripard <maxime.ripard@bootlin.com>,
Chen-Yu Tsai <wens@csie.org>, Rob Herring <robh+dt@kernel.org>
Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH v2 2/4] dt-bindings: sun4i-drm: add compatible for R40 HDMI PHY
Date: Sun, 16 Sep 2018 12:34:07 +0800 [thread overview]
Message-ID: <20180916043409.62374-3-icenowy@aosc.io> (raw)
In-Reply-To: <20180916043409.62374-1-icenowy@aosc.io>
The Allwinner R40 HDMI PHY is currently the only one that seems to be
able to select between two PLL inputs.
Add a compatible string for it, and the pll-1 clock input definition.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v2:
- Rebased when removing original A64 binding patch.
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index f8773ecb7525..dcec1a6f8ee4 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -103,6 +103,7 @@ Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
+ * allwinner,sun8i-r40-hdmi-phy
* allwinner,sun50i-a64-hdmi-phy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY
@@ -112,9 +113,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
-H3 and A64 HDMI PHY require additional clocks:
+H3, A64 and R40 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
- - pll-1: second possible phy clock parent (A64 only)
+ - pll-1: second possible phy clock parent (A64/R40 only)
TV Encoder
----------
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
To: Maxime Ripard
<maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org>,
Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Subject: [PATCH v2 2/4] dt-bindings: sun4i-drm: add compatible for R40 HDMI PHY
Date: Sun, 16 Sep 2018 12:34:07 +0800 [thread overview]
Message-ID: <20180916043409.62374-3-icenowy@aosc.io> (raw)
In-Reply-To: <20180916043409.62374-1-icenowy-h8G6r0blFSE@public.gmane.org>
The Allwinner R40 HDMI PHY is currently the only one that seems to be
able to select between two PLL inputs.
Add a compatible string for it, and the pll-1 clock input definition.
Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
---
Changes in v2:
- Rebased when removing original A64 binding patch.
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index f8773ecb7525..dcec1a6f8ee4 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -103,6 +103,7 @@ Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
+ * allwinner,sun8i-r40-hdmi-phy
* allwinner,sun50i-a64-hdmi-phy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY
@@ -112,9 +113,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
-H3 and A64 HDMI PHY require additional clocks:
+H3, A64 and R40 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
- - pll-1: second possible phy clock parent (A64 only)
+ - pll-1: second possible phy clock parent (A64/R40 only)
TV Encoder
----------
--
2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: icenowy@aosc.io (Icenowy Zheng)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/4] dt-bindings: sun4i-drm: add compatible for R40 HDMI PHY
Date: Sun, 16 Sep 2018 12:34:07 +0800 [thread overview]
Message-ID: <20180916043409.62374-3-icenowy@aosc.io> (raw)
In-Reply-To: <20180916043409.62374-1-icenowy@aosc.io>
The Allwinner R40 HDMI PHY is currently the only one that seems to be
able to select between two PLL inputs.
Add a compatible string for it, and the pll-1 clock input definition.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v2:
- Rebased when removing original A64 binding patch.
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index f8773ecb7525..dcec1a6f8ee4 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -103,6 +103,7 @@ Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
+ * allwinner,sun8i-r40-hdmi-phy
* allwinner,sun50i-a64-hdmi-phy
- reg: base address and size of memory-mapped region
- clocks: phandles to the clocks feeding the HDMI PHY
@@ -112,9 +113,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
-H3 and A64 HDMI PHY require additional clocks:
+H3, A64 and R40 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
- - pll-1: second possible phy clock parent (A64 only)
+ - pll-1: second possible phy clock parent (A64/R40 only)
TV Encoder
----------
--
2.18.0
next prev parent reply other threads:[~2018-09-16 4:35 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-16 4:34 [PATCH v2 0/4] Fix A64/R40 HDMI PHY device tree binding Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-16 4:34 ` [PATCH v2 1/4] drm: sun4i: drop second PLL from A64 HDMI PHY Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng [this message]
2018-09-16 4:34 ` [PATCH v2 2/4] dt-bindings: sun4i-drm: add compatible for R40 " Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-16 4:34 ` [PATCH v2 3/4] drm/sun4i: add support " Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-16 4:34 ` [PATCH v2 4/4] ARM: sun8i: dts: drop A64 HDMI PHY fallback compatible from R40 DT Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-16 4:34 ` Icenowy Zheng
2018-09-19 9:32 ` [PATCH v2 0/4] Fix A64/R40 HDMI PHY device tree binding Maxime Ripard
2018-09-19 9:32 ` Maxime Ripard
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