From: Boris Brezillon <boris.brezillon@bootlin.com> To: David Woodhouse <dwmw2@infradead.org>, Brian Norris <computersforpeace@gmail.com>, Boris Brezillon <boris.brezillon@bootlin.com>, Marek Vasut <marek.vasut@gmail.com>, Richard Weinberger <richard@nod.at>, linux-mtd@lists.infradead.org, Yogesh Gaur <yogeshnarayan.gaur@nxp.com>, Vignesh R <vigneshr@ti.com>, Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> Cc: Julien Su <juliensu@mxic.com.tw>, Mark Brown <broonie@kernel.org>, Mason Yang <masonccyang@mxic.com.tw>, linux-spi@vger.kernel.org, zhengxunli@mxic.com.tw Subject: [PATCH RFC 11/18] mtd: spi-nor: Prepare things for 2byte opcodes Date: Fri, 12 Oct 2018 10:48:18 +0200 [thread overview] Message-ID: <20181012084825.23697-12-boris.brezillon@bootlin.com> (raw) In-Reply-To: <20181012084825.23697-1-boris.brezillon@bootlin.com> When operating in octo mode we might have to use 2byte opcodes. Patch struct spi_nor_{read,pp}_command to take that into account. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> --- drivers/mtd/spi-nor/spi-nor.c | 26 ++++++++++++++++++-------- include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 33a07d9eb7a8..86625f1e25b3 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -200,6 +200,9 @@ static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t ofs, /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; + if (nor->read_proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + spi_nor_adjust_op(nor, &op); while (remaining) { @@ -258,6 +261,9 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t ofs, op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); + if (nor->write_proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) op.addr.nbytes = 0; @@ -2433,13 +2439,13 @@ static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor) struct spi_nor_read_command { u8 num_mode_clocks; u8 num_wait_states; - u8 opcode; - enum spi_nor_protocol proto; + u16 opcode; + u32 proto; }; struct spi_nor_pp_command { - u8 opcode; - enum spi_nor_protocol proto; + u16 opcode; + u32 proto; }; enum spi_nor_read_command_index { @@ -2499,8 +2505,7 @@ static void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states, - u8 opcode, - enum spi_nor_protocol proto) + u16 opcode, u32 proto) { read->num_mode_clocks = num_mode_clocks; read->num_wait_states = num_wait_states; @@ -2510,8 +2515,7 @@ spi_nor_set_read_settings(struct spi_nor_read_command *read, static void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, - u8 opcode, - enum spi_nor_protocol proto) + u16 opcode, u32 proto) { pp->opcode = opcode; pp->proto = proto; @@ -2887,6 +2891,9 @@ static int spi_nor_spimem_check_readop(struct spi_nor *nor, op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * op.dummy.buswidth / 8; + if (read->proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + /* * First test with 3 address bytes. The opcode itself might already * be a 4B addressing opcode but we don't care, because SPI controller @@ -2915,6 +2922,9 @@ static int spi_nor_spimem_check_progop(struct spi_nor *nor, op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto); op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto); + if (pp->proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + /* * First test with 3 address bytes. The opcode itself might already * be a 4B addressing opcode but we don't care, because SPI controller diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f80aba464eb2..5b0045720049 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -166,6 +166,8 @@ #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ +#define SNOR_PROTO_INST_2BYTE BIT(31) + #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ (SNOR_PROTO_INST(_inst_nbits) | \ SNOR_PROTO_ADDR(_addr_nbits) | \ -- 2.14.1 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@bootlin.com> To: David Woodhouse <dwmw2@infradead.org>, Brian Norris <computersforpeace@gmail.com>, Boris Brezillon <boris.brezillon@bootlin.com>, Marek Vasut <marek.vasut@gmail.com>, Richard Weinberger <richard@nod.at>, linux-mtd@lists.infradead.org, Yogesh Gaur <yogeshnarayan.gaur@nxp.com>, Vignesh R <vigneshr@ti.com>, Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> Cc: Julien Su <juliensu@mxic.com.tw>, Mason Yang <masonccyang@mxic.com.tw>, <zhengxunli@mxic.com.tw>, Mark Brown <broonie@kernel.org>, linux-spi@vger.kernel.org Subject: [PATCH RFC 11/18] mtd: spi-nor: Prepare things for 2byte opcodes Date: Fri, 12 Oct 2018 10:48:18 +0200 [thread overview] Message-ID: <20181012084825.23697-12-boris.brezillon@bootlin.com> (raw) In-Reply-To: <20181012084825.23697-1-boris.brezillon@bootlin.com> When operating in octo mode we might have to use 2byte opcodes. Patch struct spi_nor_{read,pp}_command to take that into account. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> --- drivers/mtd/spi-nor/spi-nor.c | 26 ++++++++++++++++++-------- include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 33a07d9eb7a8..86625f1e25b3 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -200,6 +200,9 @@ static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t ofs, /* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; + if (nor->read_proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + spi_nor_adjust_op(nor, &op); while (remaining) { @@ -258,6 +261,9 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t ofs, op.addr.buswidth = spi_nor_get_protocol_addr_nbits(nor->write_proto); op.data.buswidth = spi_nor_get_protocol_data_nbits(nor->write_proto); + if (nor->write_proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second) op.addr.nbytes = 0; @@ -2433,13 +2439,13 @@ static int s3an_nor_scan(const struct flash_info *info, struct spi_nor *nor) struct spi_nor_read_command { u8 num_mode_clocks; u8 num_wait_states; - u8 opcode; - enum spi_nor_protocol proto; + u16 opcode; + u32 proto; }; struct spi_nor_pp_command { - u8 opcode; - enum spi_nor_protocol proto; + u16 opcode; + u32 proto; }; enum spi_nor_read_command_index { @@ -2499,8 +2505,7 @@ static void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states, - u8 opcode, - enum spi_nor_protocol proto) + u16 opcode, u32 proto) { read->num_mode_clocks = num_mode_clocks; read->num_wait_states = num_wait_states; @@ -2510,8 +2515,7 @@ spi_nor_set_read_settings(struct spi_nor_read_command *read, static void spi_nor_set_pp_settings(struct spi_nor_pp_command *pp, - u8 opcode, - enum spi_nor_protocol proto) + u16 opcode, u32 proto) { pp->opcode = opcode; pp->proto = proto; @@ -2887,6 +2891,9 @@ static int spi_nor_spimem_check_readop(struct spi_nor *nor, op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * op.dummy.buswidth / 8; + if (read->proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + /* * First test with 3 address bytes. The opcode itself might already * be a 4B addressing opcode but we don't care, because SPI controller @@ -2915,6 +2922,9 @@ static int spi_nor_spimem_check_progop(struct spi_nor *nor, op.addr.buswidth = spi_nor_get_protocol_addr_nbits(pp->proto); op.data.buswidth = spi_nor_get_protocol_data_nbits(pp->proto); + if (pp->proto & SNOR_PROTO_INST_2BYTE) + op.cmd.nbytes = 2; + /* * First test with 3 address bytes. The opcode itself might already * be a 4B addressing opcode but we don't care, because SPI controller diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index f80aba464eb2..5b0045720049 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -166,6 +166,8 @@ #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ +#define SNOR_PROTO_INST_2BYTE BIT(31) + #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \ (SNOR_PROTO_INST(_inst_nbits) | \ SNOR_PROTO_ADDR(_addr_nbits) | \ -- 2.14.1
next prev parent reply other threads:[~2018-10-12 8:48 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-12 8:48 [PATCH RFC 00/18] mtd: spi-nor: Proposal for 8-8-8 mode support Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 01/18] mtd: spi-nor: Add a flash_info entry for Macronix mx25uw51245g Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 02/18] spi: Prepare things for octo mode support Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 03/18] spi: spi-mem: Prepare things for DTR " Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 04/18] spi: spi-mem: Prepare things for dual bytes opcodes support Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 05/18] spi: spi-mem: mxic: Add support for DTR and Octo mode Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-11-18 17:21 ` Miquel Raynal 2018-11-18 17:21 ` Miquel Raynal 2018-11-18 17:32 ` Boris Brezillon 2018-11-18 17:32 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 06/18] mtd: spi-nor: Move m25p80 code in spi-nor.c Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 07/18] mtd: spi-nor: Rework hwcaps selection for the spi-mem case Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 08/18] mtd: spi-nor: Define the DPI, QPI and OPI hwcaps Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 09/18] mtd: spi-nor: Add spi_nor_{read, write}_reg() helpers Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 10/18] mtd: spi-nor: Add support for X-X-X modes Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon [this message] 2018-10-12 8:48 ` [PATCH RFC 11/18] mtd: spi-nor: Prepare things for 2byte opcodes Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 12/18] mtd: spi-nor: Provide a hook to tweak flash parameters Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 13/18] mtd: spi-nor: Add 8-8-8 mode support to Macronix mx25uw51245g Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 14/18] mtd: spi-nor: Clarify where DTR mode applies Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 15/18] mtd: spi-nor: Add DTR support to the spi-mem logic Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 16/18] mtd: spi-nor: Add the concept of full DTR modes Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 17/18] mtd: spi-nor: Add 8D-8D-8D mode Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon 2018-10-12 8:48 ` [PATCH RFC 18/18] mtd: spi-nor: Make sure the 8D-8D-8D can be selected on mx25uw51245g Boris Brezillon 2018-10-12 8:48 ` Boris Brezillon [not found] ` <OF300145A1.D60E7B33-ON48258376.002EDC4B-48258376.0031A14C@LocalDomain> [not found] ` <OF3005248A.454B9B59-ON48258382.002767AE-48258382.00293E8D@mxic.com.tw> 2019-01-14 8:39 ` Boris Brezillon 2019-01-14 8:39 ` Boris Brezillon 2018-10-19 12:25 ` [PATCH RFC 00/18] mtd: spi-nor: Proposal for 8-8-8 mode support Mark Brown 2018-10-19 12:25 ` Mark Brown 2018-10-19 12:59 ` Boris Brezillon 2018-10-19 12:59 ` Boris Brezillon 2018-10-21 13:36 ` Mark Brown 2018-10-21 13:36 ` Mark Brown 2018-10-22 8:21 ` Boris Brezillon 2018-10-22 8:21 ` Boris Brezillon 2018-10-22 12:01 ` Mark Brown 2018-10-22 12:01 ` Mark Brown
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