From: Chris Packham <chris.packham@alliedtelesis.co.nz> To: linux@armlinux.org.uk Cc: u.kleine-koenig@pengutronix.de, jlu@pengutronix.de, bp@alien8.de, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Chris Packham <chris.packham@alliedtelesis.co.nz> Subject: [PATCH v5 0/8] EDAC drivers for Armada XP L2 and DDR Date: Mon, 29 Oct 2018 20:25:27 +1300 [thread overview] Message-ID: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> (raw) The current plan is for these to go in via the ARM tree once appropriate Reviews/Acks have been given. This series adds drivers for the L2 cache and DDR RAM ECC functionality as found on the MV78230/MV78x60 SoCs. Jan has tested these changes with the MV78460 (on a custom board with a DDR3 ECC DIMM), Chris has tested these changes with 88F6820 and 98dx3236 (both a custom boards with fixed DDR3 + ECC). Also contained in this series is an additional debugfs wrapper. Compared to the previous v4 series I've added my s-o-b to some of Jan's patches and rebased against v4.19.0. Compared to the previous v3 series, the following changes have been made: - Use shorter names for the AURORA ECC and parity registers - Numerous formatting changes to edac/armada_xp.c (as requested by Boris) - Added support for Armada-38x and 98dx3236 SoCs Compared to the previous v2 series, the following changes have been made: - Allocate EDAC structures later during probing and drop devres support patches (requested by Boris) - Make drvdata->width usage consistent according to the comment (suggested by Chris) Compared to the previous v1 series, the following changes have been made: - Add the aurora-l2 register defines earlier in the series (suggested by Russell King and Gregory CLEMENT ) - Changed the DT vendor prefix from "arm" to "marvell" for the ecc-enable/disable properties on the aurora-l2 (suggested by Russell King) - Fix some warnings reported by checkpatch Compared to the original RFC series, the following changes have been made: - Integrated Chris' patches for parity and ECC configuration via DT - Merged the DDR RAM and L2 cache drivers (as requested by Boris, analogous to fsl_ddr_edac.c and mpc85xx_edac.c) - Added myself to MAINTAINERS (requested by Boris) - L2 cache: Track the msg size and use snprintf (review comment by Chris) - L2 cache: Split error injection from the check function (review comment by Chris) - DDR RAM: Allow 16 bit width in addition to 32 and 64 bit (review comment by Chris) - Use of_match_ptr() (review comments by Chris) - Minor checkpatch cleanups Chris Packham (3): ARM: l2x0: support parity-enable/disable on aurora ARM: l2x0: add marvell,ecc-enable property for aurora EDAC: armada_xp: Add support for more SoCs Jan Luebbe (5): ARM: l2c: move cache-aurora-l2.h to asm/hardware ARM: aurora-l2: add prefix to MAX_RANGE_SIZE ARM: aurora-l2: add defines for parity and ECC registers EDAC: Add missing debugfs_create_x32 wrapper EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC .../devicetree/bindings/arm/l2c2x0.txt | 2 + MAINTAINERS | 6 + .../asm/hardware}/cache-aurora-l2.h | 50 +- arch/arm/mm/cache-l2x0.c | 20 +- drivers/edac/Kconfig | 7 + drivers/edac/Makefile | 1 + drivers/edac/armada_xp_edac.c | 644 ++++++++++++++++++ drivers/edac/debugfs.c | 11 + drivers/edac/edac_module.h | 5 + 9 files changed, 742 insertions(+), 4 deletions(-) rename arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h (50%) create mode 100644 drivers/edac/armada_xp_edac.c -- 2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: chris.packham@alliedtelesis.co.nz (Chris Packham) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 0/8] EDAC drivers for Armada XP L2 and DDR Date: Mon, 29 Oct 2018 20:25:27 +1300 [thread overview] Message-ID: <20181029072535.31667-1-chris.packham@alliedtelesis.co.nz> (raw) The current plan is for these to go in via the ARM tree once appropriate Reviews/Acks have been given. This series adds drivers for the L2 cache and DDR RAM ECC functionality as found on the MV78230/MV78x60 SoCs. Jan has tested these changes with the MV78460 (on a custom board with a DDR3 ECC DIMM), Chris has tested these changes with 88F6820 and 98dx3236 (both a custom boards with fixed DDR3 + ECC). Also contained in this series is an additional debugfs wrapper. Compared to the previous v4 series I've added my s-o-b to some of Jan's patches and rebased against v4.19.0. Compared to the previous v3 series, the following changes have been made: - Use shorter names for the AURORA ECC and parity registers - Numerous formatting changes to edac/armada_xp.c (as requested by Boris) - Added support for Armada-38x and 98dx3236 SoCs Compared to the previous v2 series, the following changes have been made: - Allocate EDAC structures later during probing and drop devres support patches (requested by Boris) - Make drvdata->width usage consistent according to the comment (suggested by Chris) Compared to the previous v1 series, the following changes have been made: - Add the aurora-l2 register defines earlier in the series (suggested by Russell King and Gregory CLEMENT ) - Changed the DT vendor prefix from "arm" to "marvell" for the ecc-enable/disable properties on the aurora-l2 (suggested by Russell King) - Fix some warnings reported by checkpatch Compared to the original RFC series, the following changes have been made: - Integrated Chris' patches for parity and ECC configuration via DT - Merged the DDR RAM and L2 cache drivers (as requested by Boris, analogous to fsl_ddr_edac.c and mpc85xx_edac.c) - Added myself to MAINTAINERS (requested by Boris) - L2 cache: Track the msg size and use snprintf (review comment by Chris) - L2 cache: Split error injection from the check function (review comment by Chris) - DDR RAM: Allow 16 bit width in addition to 32 and 64 bit (review comment by Chris) - Use of_match_ptr() (review comments by Chris) - Minor checkpatch cleanups Chris Packham (3): ARM: l2x0: support parity-enable/disable on aurora ARM: l2x0: add marvell,ecc-enable property for aurora EDAC: armada_xp: Add support for more SoCs Jan Luebbe (5): ARM: l2c: move cache-aurora-l2.h to asm/hardware ARM: aurora-l2: add prefix to MAX_RANGE_SIZE ARM: aurora-l2: add defines for parity and ECC registers EDAC: Add missing debugfs_create_x32 wrapper EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC .../devicetree/bindings/arm/l2c2x0.txt | 2 + MAINTAINERS | 6 + .../asm/hardware}/cache-aurora-l2.h | 50 +- arch/arm/mm/cache-l2x0.c | 20 +- drivers/edac/Kconfig | 7 + drivers/edac/Makefile | 1 + drivers/edac/armada_xp_edac.c | 644 ++++++++++++++++++ drivers/edac/debugfs.c | 11 + drivers/edac/edac_module.h | 5 + 9 files changed, 742 insertions(+), 4 deletions(-) rename arch/arm/{mm => include/asm/hardware}/cache-aurora-l2.h (50%) create mode 100644 drivers/edac/armada_xp_edac.c -- 2.19.1
next reply other threads:[~2018-10-29 7:26 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-10-29 7:25 Chris Packham [this message] 2018-10-29 7:25 ` [PATCH v5 0/8] EDAC drivers for Armada XP L2 and DDR Chris Packham 2018-10-29 7:25 ` [PATCH v5 1/8] ARM: l2c: move cache-aurora-l2.h to asm/hardware Chris Packham 2018-10-29 7:25 ` Chris Packham 2018-10-29 7:25 ` [v5,1/8] " Chris Packham 2018-10-29 7:25 ` [PATCH v5 2/8] ARM: aurora-l2: add prefix to MAX_RANGE_SIZE Chris Packham 2018-10-29 7:25 ` Chris Packham 2018-10-29 7:25 ` [v5,2/8] " Chris Packham 2018-10-29 7:25 ` [PATCH v5 3/8] ARM: aurora-l2: add defines for parity and ECC registers Chris Packham 2018-10-29 7:25 ` Chris Packham 2018-10-29 7:25 ` [v5,3/8] " Chris Packham 2018-10-29 7:25 ` [PATCH v5 4/8] ARM: l2x0: support parity-enable/disable on aurora Chris Packham 2018-10-29 7:25 ` Chris Packham 2018-10-29 7:25 ` [v5,4/8] " Chris Packham 2018-10-29 7:25 ` [PATCH v5 5/8] ARM: l2x0: add marvell,ecc-enable property for aurora Chris Packham 2018-10-29 7:25 ` Chris Packham 2018-10-29 7:25 ` [v5,5/8] " Chris Packham 2018-10-30 19:31 ` [PATCH v5 5/8] " Rob Herring 2018-10-30 19:31 ` Rob Herring 2018-10-30 19:31 ` Rob Herring 2018-10-30 19:31 ` [v5,5/8] " Rob Herring 2018-11-08 15:17 ` [PATCH v5 5/8] " Borislav Petkov 2018-11-08 15:17 ` Borislav Petkov 2018-11-08 15:17 ` [v5,5/8] " Borislav Petkov 2018-10-29 7:25 ` [PATCH v5 6/8] EDAC: Add missing debugfs_create_x32 wrapper Chris Packham 2018-10-29 7:25 ` Chris Packham 2018-10-29 7:25 ` [v5,6/8] " Chris Packham 2018-10-29 7:25 ` [PATCH v5 7/8] EDAC: Add driver for the Marvell Armada XP SDRAM and L2 cache ECC Chris Packham 2018-10-29 7:25 ` Chris Packham 2018-10-29 7:25 ` [v5,7/8] " Chris Packham 2018-10-29 7:25 ` [PATCH v5 8/8] EDAC: armada_xp: Add support for more SoCs Chris Packham 2018-10-29 7:25 ` Chris Packham 2018-10-29 7:25 ` [v5,8/8] " Chris Packham
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20181029072535.31667-1-chris.packham@alliedtelesis.co.nz \ --to=chris.packham@alliedtelesis.co.nz \ --cc=bp@alien8.de \ --cc=jlu@pengutronix.de \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-edac@vger.kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux@armlinux.org.uk \ --cc=u.kleine-koenig@pengutronix.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.